Did you tried on DVK board or custom board? It looks 0.028mV is not bad with strong drive low level. Any concern over this?
Are P6.0 or P6.1 connected to an external component (such as a resistor) pulled up to a voltage?
If so, then the voltage low offset is due to the current flowing through the output of these pins.
If you've got a very good GND connection in your measurement where are some reasons for the voltage offset:
- Your output is connected to other connections (external resistor for instance) pulled up to some voltage. This would cause some current to flow in the circuit which includes the low FET driving the output. Since no FET is 0 ohms, the voltage across the low-side FET of the port would be: V = Rds_low_fet * Icircuit.
- You're using a oscilloscope. Oscilloscopes are great tools but it is usually not your most accurate tool in the toolbox. Many oscilloscopes use 8-bit ADCs. The ADC effective range is designed to span the full visible vertical resolution. Therefore if your scope is set for 1V/div and there are 10 vertical divisions, the 8-bit (256 ADC counts) are divided even across the 10V vertical. Therefore 1 ADCcount = 10V/256counts = 39mV/ADCcount. This is more than your 28mV offset.
If the signal is constant, a multimeter is usually more accurate.
Thanks for your relpy, the problem has been resolved. Yesterday I use the customer 's core board for testing, today I test on the 62-BLE, it's OK, only 1mV, check with the cutstomer carefully, there are more pull up resistance 4.7K connect to VDD3.3V. becaues P60/1 is the I2C master , and connect to a slaver , when go to power mode, the slaver need power off, if P60/1 pull up to 3.3V, there will have fill current to slaver. If set P6.0/1 to GND, there will add current from the 4.7K pull up resistance.