In the "PSoC 4100M/4200M Family PSoC 4 Architecture TRM, Document No. 001-95223" there is a description about the "1.8V CMOS" input as follows.
And the threshold is in the device datasheet. It should be in the datasheet, but I cannot find the specification.
4200M has three power domains assigned to each ports as follows.
And there power domains are independent as described in the "9. Power Supply and Monitoring" section.
If you can assign one of these power domain to 1.8V, the port will be used for 1.8V interface.
Thanks for pointed me to the related trm section. I couldn't had noticed before. Maybe I had looked 4200 trm instead of 4200M before.
There are a few unclear points now;
I tried this in Psoc Creator;
Set the supplies as: VDDD=VDDA=3.8V and VDDIO=1.8V
I want to use Port0 and Port1 as 3.8V IO and Port3 as 1.8V IO.
1- I added 3 output pins located at Port0, Port1 and Port3.
But only "VDDIO" drive level option is exist in the pin settings for all the pins.
In this condition, Are all the Output pins at 1.8V level or Port0/Port1 pins at 3.8V level?
2- For example all the ports consumed except Port2 (VDDDA - 3.8V level) and one more 1.8V input needed.
Psoc creator let the "CMOS 1.8V" input threshold setting for a Port2 pin and builds without any error/warning.
In this condition, Can a Port2 pin be used as 1.8V level input?
3- Is there any difference between following input combinations?
- Port2 (VDDDA - 3.8V level) pin and "CMOS 1.8V" threshold selection
- Port3 (VDDIO - 1.8V level) pin and "CMOS 1.8V" threshold selection
- Port3 (VDDIO - 1.8V level) pin and "CMOS " threshold selection
1) In this condition, Are all the Output pins at 1.8V level or Port0/Port1 pins at 3.8V level?
Ans: The output pin will be on the IO supply source of the port as per the table. Some other devices and SIO pins have an ability to take a Vref input. That is why an option is available in the field.
2) In this condition, Can a Port2 pin be used as 1.8V level input?
Ans: Irrespective of the output driver source, all the pins can use CMOS 1.8V input buffer.
3)Is there any difference between following input combinations?
Ans: Pins with other voltage levels can also use the input buffer of CMOS 1.8V. For ports output driver which are driven using different sources, the output voltage will depend on the source( VDDA or VDDIO according to the port ).
Thanks for the clarification, this is the answer of my question.
I want to ask one more question, not so related this thread but still a 1.8V issue.
Sorry for my endless questions.
SWD port supplied by VDDIO (1.8V) and XRES pin is supplied by VDDD (3.8V).
Is this level difference OK for the debugger (kitprog or miniprog) ?
I couldn't have found any info about whether the debugger drives the XRES pin as "open drain".
If XRES not driven by an open drain debugger pin this should be a problem.
So I converted the XRES pin level to 1.8V by a transistor. Please check the attached schematic.
Is this true way to do it or Am I missing something?
swd_port.png 57.4 K
It would be if you could post different questions in a different thread as this will get better attention from the community. XRES pin is internally pulled up to VDDD.
As you are only pulling down the pin other wise it should be alright without the arrangement.