Q) According to AN211622 document I can not find max trace length of the any design?
Ans) All I/O are length-matched and 50 ohm impedance controlled
Which type of buffer can I use (hyperram pins connected to bank 34 lvcmos33 pins)?
Ans) Yes we use lvcmos33. The tool auto instantiate IO buffers per the architecture requirements. In case of HyperRAM, we have custom instances of ODDR/IDDR and IDELAY logic for DQS and IO, but these will typically be before(for outputs)/ after(for inputs) of the auto generated IO buffers. Making FPGA work at max HyperRAM frequency will require some careful thinking of capture logic for read with proper delay setting between IO and DQS.