1 2 Previous Next 16 Replies Latest reply on Jun 11, 2020 4:44 PM by DaKn_263916

    Verilog Error

    DaKn_263916

      Trying to create a basic SIPO 64 bit shift register.

       

      I am a newbee to Verilog, and this error causing me grief. I thought that

      you can declare a wide output in Module naming, then in body declare it as a

      reg so it picks up symbol name of output in order to bring out to pins.

       

      Error occurs on line shown -

       

      PSOC Verilog Errors 1.JPG

       

      PSOC Verilog Errors.JPG

       

      Regards, Dana.

        • 1. Re: Verilog Error
          MoTa_728816

          Hi,

           

          When I tried with CY8CKIT-044 (4200M)

          the compiler did not like to have multiple posedges, so I changed them as level input (SetAll, ClrAll)

          Meantime, 64bit was too much, even with 16 bit I got error (not enough UDB) , so far, I only get success with 8bit (orz)

          000-Verilog.JPG

          May be, your mileage vary for a bigger device.

           

          moto

          1 of 1 people found this helpful
          • 2. Re: Verilog Error
            DaKn_263916

            Thnak you Mr. Tanaka, got me a good start. The posedge I am guessing had to be level because when

            I did symbol I did not declare it of clock type.

             

            I used a PSOC 5LP and it routes all 64 bits.

             

            Thanks again, made my day.

             

            Regards, Dana.

            • 3. Re: Verilog Error
              BoTa_264741

              Dana,

              Attached is project with 64-bit reg compiled for PSoC5. The code is similar to the Motoo, but not same. Design takes about 30% of resources. The load and reset must be synchronous, or reset can be set to async while the load is sync for Verilog to compile.

              /odissey1

               

              P.S. While creating the component I encountered a problem. I originally named the component ShiftReg, and component disappeared from the list of components. It won't appear even after renaming the component and clearing the fitter file. It appears that "ShiftReg" is a reserved name and can not be used. Had to re-create component from scratch under new name ShiftReg64.

              2 of 2 people found this helpful
              • 4. Re: Verilog Error
                RodolfoG_11

                You guys will be way better off to implement a 64-bit ShiftRegister with datapaths. This probably can be done using 4 datapaths and a few PLDs. You can use A0 and A1 to store the shifted bits.

                • 5. Re: Verilog Error
                  BoTa_264741

                  RodolfoG,

                  I think it highlights the major issue with PSoC: for casual user implementing staff using Datapath takes 10x more time than in Verilog.

                  /odissey1

                  • 6. Re: Verilog Error
                    RodolfoG_11

                    That's why is important to flourish a community to create these components, so they can be used out-of-shelf by other users. We acknowledge that developing components with datapath is not easy, so only a few key users are able to do so.

                    • 7. Re: Verilog Error
                      MoTa_728816

                      Hi,

                       

                      I'm sorry but I have not been brave enough to challenge that field, yet.

                      I (or we) would appreciate it if you teach us how to implement a 64 bit shift_register here,

                      so that it will give us a chance to start studying it.

                       

                      moto

                      • 8. Re: Verilog Error
                        RodolfoG_11

                        I would start with an 8-bit shift register to understand how to do it. This AppNote is a good start:

                        https://www.cypress.com/documentation/application-notes/an82156-psoc-3-psoc-4-and-psoc-5lp-designing-psoc-creator-compon…

                        It doesn't explain exactly how to implement a shift register with datapath, but it gives a good overall how to use a datapath.

                        1 of 1 people found this helpful
                        • 9. Re: Verilog Error
                          MoTa_728816

                          Hi,

                           

                          Thank you.

                          I will study it later.

                           

                          moto

                          • 10. Re: Verilog Error
                            DaKn_263916

                            Whats the impact on shifting speed, straight Verilog vs DataPath ?

                             

                            Regards, Dana.

                            • 11. Re: Verilog Error
                              DaKn_263916

                              Question, if load and clr signals declared as inputs in symbol wizard, that

                              means they are synched to clock input ?

                               

                              Whereas if I declared them as clock signals in symbol wizard and then

                              used them in trigger as posedge then they would be asynch, correct ?

                               

                              Regards, Dana.

                              • 12. Re: Verilog Error
                                BoTa_264741

                                Dana,

                                > if load and clr signals declared as inputs in symbol wizard, that means they are synched to clock input ?

                                -No. The load and clr are not synced to anything. They are just input wires, it is up to developer to decide how to use them.

                                If declared as a clock, it is just another signal of same status as load or clr. Nothing special.

                                 

                                >Whats the impact on shifting speed, straight Verilog vs DataPath ?

                                The project provided above gives max BUS_CLK of 83MHz. The issue with chained Datapath is that max operation clock is slowly degrading with the number of DPs. For example, take a look at the Timer/Counter/PWM as bit depth increases 8,16,24,32-bits. I haven't seen any component with more that 4 chained DP (32-bit), and 64-bit shift register needs 8 chained DPs. I don't know if this is fundamental restriction or not.

                                 

                                Please let us know what extra options you need to complete the component, like you mentioned a rising edge for clr, etc.

                                /odissey1

                                • 13. Re: Verilog Error
                                  RodolfoG_11

                                  Cypress Datapath Configurator tool only allows chaining 4 datapath, but you can manually chain two 32-bit datapath to create a 64-bit shift register.

                                   

                                  Dana, what do you plan to do with the 64-bit output register? Connect to pins? To status register? And how fast does your application need to shift?

                                   

                                  If you are connecting to a status register, you should definitely use a datapath to implement this.

                                  • 14. Re: Verilog Error
                                    DaKn_263916

                                    This was just an exercise for me to learn Verilog.

                                     

                                    I also just finished a 64 bit cntr, was curious how to get cntr value into

                                    C code for processing, used status registers to do that. Interesting

                                    max clk freq wound up < 18 Mhz, All the routes must have burdened

                                    some specific route to cause a lot of delay.

                                     

                                    Cntr64.JPG

                                     

                                    Thnaks all for the help, now I know about 1% on Verilog, seriously dangerous at this point.

                                    Maybe I can do an elevator design.....:)

                                     

                                    Regards, Dana.

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