Hello, I am having problems with the classic stuck I2C slave problem. The PSoC 5LP is the master, and if we get a glitch on the bus, the slave get stuck waiting for a clock pulse, and may hold the SDA line low. The solution is to toggle extra pulses on the SCL pin until the slave I2C slave device is synced back up and releases the SDA pin.
I am am trying to implement this recovery routine, but I am having trouble taking over the SCL pin and using the I2C_SCL_Write() and I2C_SCL_Read() functions. There must be a register that connects these pins to either the UDB I2C implementation of the FF I2C implementation. On the PSoC 4 forum, this function is listed as:
But CYREG_HSIOM_PORT_SEL4 does not exist on the PSoC 5LP. Any help with how to do this would be greatly appreciated.