The clock input frequency should be greater than or equal to 10x the maximum A or B input frequency.Y
The best practice is to set the QuadDec input clock frequency as high as possible.
Do you have any restriction for keeping this clock frequency high? If yes, what is the limit?
I set the clock to 50Hz, but the data read through the "QuadDec_Hall_ReadCounter" API is always 32678.
I don't know if the clock configuration is incorrect or the other configuration is incorrect？
>>"I set the clock to 50Hz, but the data read through the "QuadDec_Hall_ReadCounter" API is always 32678."
--> The input clock frequency of QuadDec should be greater than or equal to 7 KHz since the frequency of PhiA and PhiB are 700Hz (as per 10x rule).
>>Please check the "Quadrature_Decoder" code example from PSoC Creator. You can use this project as a reference to test your board.
Kindly update if you have any queries once you have gone through the code example.
Thanks and regards