5 Replies Latest reply on Jun 24, 2020 3:30 AM by PradiptaB_11

    Mirror sram

    AbSh_2443496

      Hi,

      I am using CY62177EV30LL in one of our applications and we would like to use two of these chips for increased memory.

      In terms of layout, I am thinking, can we place one on the top layer and one on the bottom layer? We would swap the address and data lines (so that we can connect them through same vias), but because access is random, it should not matter, right?

      I am attaching my proposed schematic. Only exception would be I/O11 and I/O15, which cannot be mirrored.

      Has anyone here done that and would any of you be able to suggest if there should be any concerns.

       

      Thanks,

      AQ

        • 1. Re: Mirror sram
          PradiptaB_11

          Hi,

           

          You can place the memory on top and bottom sides of the board. It allows the layout to share vias on address and data pins, reducing trace length and simplifying routing. The data bus pins on a memory device may be swapped if the memory is operating in a word mode since it does not matter which data bit is connected to a particular bit on the controller. The address lines may also be swapped to simplify layout. If the memory is running as a word access, any line may be swapped. Stress keeping all trace lengths equal to improve timing margins.  All signals to the part that are latched by a clock should have the same length, not just address and data bus.

           

          Thanks,

          Pradipta.

          1 of 1 people found this helpful
          • 2. Re: Mirror sram
            AbSh_2443496

            Thanks Pradipta for a reply.

            In your reply, you mentioned clock, but this is async memory, so we do not have clock.

             

            Pertaining to the same layout, I had another question. I assume I can use the highest address bit to offer depth expansion for these two memories (4MB + 4MB). So question here. I assume I need to use this highest address bit as a chip select to both the memories. But would it be ok to use such? In terms of timings, #CS goes low followed by Address appearing on the bus. If one address bit behaves as CS, would that still be fine?

             

            thanks,

            AQ

            • 3. Re: Mirror sram
              PradiptaB_11

              Hi,

               

              Yes, for Async no need for clock.

              The device has specifically two Chip Select pins for depth expansion to be made use of. Is it not possible to use on the CS pins for this purpose.

               

              Thanks,

              Pradipta.

              • 4. Re: Mirror sram
                AbSh_2443496

                That makes so much sense now. I always wondered why two chip selects. So can you confirm the configuration that I have attached would work?

                 

                Thanks for the help,

                AQ

                • 5. Re: Mirror sram
                  PradiptaB_11

                  Hi,

                   

                  Yes, The attached configuration will work.

                   

                  Thanks,

                  Pradipta.