When I tried with PSoC Creator at first I got following error.
It seems that USBDM can be either CMOS_OUTPUT or HI_Z_ANALOG.
So I changed the pin to Hi-Z analog.
Since it's an analog input, I think that we need some trick to make it readable from the digital side.
So how about trying something like below?
(I have not tested it as I don't have a board with this MCU)
Thanks for the reply moto.
I'm using PSoC Creator 18.104.22.1685 and those errors don't appear for me.
I'm happy to post my project too, if that is helpful and allowed on these forums.
The MCU has all other pins accounted for in our product, so using a USB pin as a GPIO Input would be a quick fix to a problem we are having.
I'm sorry for my insufficient description.
I'm also using PSoC Creator 4.3 (22.214.171.1245).
First of all, I got the error when I set the pin as "Digital Input Resistive Pull Up"
The error message was
Error: plm.M0046: E2728: <EXT_GPIO5(0)> cannot be placed at <P14> because USB pins do not support drive modes other than CMOS_OUT and HI_Z_ANALOG.
So I assumed that the only valid choice(s) were either "CMOS_OUT" or "HI_Z_ANALOG" in the previous reply.
I also tried
(1) High Impedance Digital
(2) High Impedance Analog
Then to make the analog signal readable from the digital, I connected it through comparator to status register
As the circuit it seemed fine, but as I tried to compile, I got the following error.
Error: fit.M0059: FFB and IO placement failed: Invalid pin assignment USBDM. This pin does not support ANALOG. (App=cydsfit)
So, although the first error message suggested that USBDM supports only CMOS_OUT and HI-Z-Analog,
the only choice the PSoC Creator allows is HI-Z-Digital, which you are using.
Then in the PSoC 63 with BLE Architecture Technical Reference Manual (TRM),
I found following lines
126.96.36.199 GPIO Mode Logic
The D+ and D– pins can be used either as GPIO pins or
USB I/O pins. This is controlled by the IOMODE bit of the
USBDEV_USBIO_CR1 register. This bit should be set HIGH
for GPIO functionality and LOW for USB operation.
In the PSoC 63 with BLE Registers Technical Reference Manual (TRM)
So, how about trying
*(uint32_t *)CYREG_USBFS0_USBDEV_USBIO_CR1 |= (0x01 << CYFLD_USBFS_USBDEV_IOMODE__OFFSET) ;
Below two registers should be configured to enable use USBIO as GPIO input pin.
/*Set USBIO to GPIO mode*/
*(uint32 *)CYREG_USBFS0_USBDEV_USBIO_CR1 |= (0x01u << CYFLD_USBFS_USBDEV_IOMODE__OFFSET);
/* Set GPIO input enable */
*(uint32 *)CYREG_USBFS0_USBLPM_USBIO_CTL |= ((0x01u << CYFLD_USBFS_USBLPM_DM_P__OFFSET) | (0x01u << CYFLD_USBFS_USBLPM_DM_M__OFFSET));