1 Reply Latest reply on May 28, 2020 1:33 AM by NoriakiT_91

    FRAM FM25V10 read access

    rust_4710131

      As the datasheet "001-84499_FM25V10_1_Mbit_128K_X_8_Serial_SPI_F_RAM.pdf" describes :

      The read access is as on the attached picture.

       

      FM25V10_ReadTiming2.png

      So Bit 23 (the 24th) is the last bit written, on the rising slope of SCK. The 1st read data bit D7 is available upon the falling slope of the same SCK pulse, which is somewhat unusual. Especially since the last bit read (D0) is available  on the falling 6th read-SCK. The 7th read-SCK is for nothing.

      In my opinion, SO line should be shifted by one SCK to the right. Such that the bit D7 is available after the falling 0th read-SCK. And eventuall the last bit, D0, is available after the falling read-SCK7.


      Please confirm and adjust the datasheet.

        • 1. Re: FRAM FM25V10 read access
          NoriakiT_91

          Please refer another timing chart in the AC Switching Characteristics as follows.

          GS004758.png

          The input port SI is captured at the rising edge of the SCK and the output port SO changes its state at the falling edge of the SCK.  In the Memory Read Operation case, A0 is captured at the rising edge of the SCK pulse #23 and the D0 is driven at the falling edge of the SCK pulse #23.  The F-RAM get the data during the SCK pulse #23 is high, t_CH.  The minimum t_CH is 11ns for VDD=3.3V.

           

          Regards,

          Noriaki