Please refer another timing chart in the AC Switching Characteristics as follows.
The input port SI is captured at the rising edge of the SCK and the output port SO changes its state at the falling edge of the SCK. In the Memory Read Operation case, A0 is captured at the rising edge of the SCK pulse #23 and the D0 is driven at the falling edge of the SCK pulse #23. The F-RAM get the data during the SCK pulse #23 is high, t_CH. The minimum t_CH is 11ns for VDD=3.3V.