We don't provide tools to simulate the logic in the schematics. But what you can do is to probe any signal to an output pin, so you can use a logic analyzer to verify the logic.
For a real simulation, instead of using logic in the schematics, you could use the Verilog code generated by the components. You can do RTL simulation with tools like ModelSim. We provide RTL code for all the primitive IPs you can use in UDBs, like datapath, control registers, status registers and so on.
Is there enough information available in a PSoC Creator design to allow a Application to be created covert a UDB/Datapath design into a netlist for PSpice?
All the simulation files are located here:
C:\Program Files (x86)\Cypress\PSoC Creator\4.x\PSoC Creator\warp\lib\sim
If you want to get the overall chip design for the project, search for the *.v file in codegentemp folder.