5 Replies Latest reply on Aug 1, 2020 1:43 AM by ReMa_3807036

    PSoC4100S SPCIF interrupt management to write flash row

    ReMa_3807036

      Hi,

      I'm following the example in "PSoC 4100S and PSoC 4100S Plus - PSoC 4 Architecture Technical Reference Manual (TRM)" (par.27.7), to write flash avoiding the blocking; infact the erase/write operation in flash required about 12-20ms, and during this time the CPU is stopped there.

      The example shows the mode to avoid this blocking, in particular it is necessary to run code in sram (at least the routines used for the scope) also the interrupt service routine for SPC has to be in sram.

       

      In my project (here attached), I was able to move the routine in sram, I define also the SPC interrupt and redirect its vector address, but this interrupt never happens,  I try to read the register CPUSS SYSARG to check the error code, but with Miniprog3 debugger this register seems to be not readable (I see #######... instead of value), but I can access to CPUSS SYSREQ , there I read the last command sent (0x00000007) really with bit31 =0, the command had bit31=1, seems that it becomes 0 due to interrupt management, the question is who, where?.

       

      In the original example is required to have Clock to 48MHz, but the device I'm using CY8C4125AXI-S433 has 24MHz as max value, could be it the problem?

       

      Someone has had similar problems?

      Thanks in advance

       

      Renato

        • 1. Re: PSoC4100S SPCIF interrupt management to write flash row
          DheerajK_81

          Hello Renato,

           

          As shown in the example, you need to set the CPUSS_CONFIG_REG to 0x01 because SPC ISR should be in SRAM. I don't see this in your implementation. Please add this and check if it works.

           

          Can you try doing this and checking if you see the value of the CPUSS_SYSARG register?

          volatile uint32_t value = CY_GET_REG32(CPUSS_SYSARG_REG);

           

          Check the status after each system call to see where it fails. When the failure occurs compare the error status with the Section 27.6 System Call Status table in the Architecture TRM to see what caused the error.

           

          Regards,

          Dheeraj

          • 2. Re: PSoC4100S SPCIF interrupt management to write flash row
            ReMa_3807036

            Hi Dheeraj,

            thanks for support.

            Really I had tried to set CPUSS_CONFIG_REG to 0x01 without luck, it should be to use sram "vector table" instead of flash, this register seems to be not present in this micro (PSoC 4 Registers Technical Reference Manual (TRM) par.6.1), for this micro this function should be provided by VTOR register (Vector Table Offset Reg.), I have checked and it contains the right information to use sram 0x20000000 address for vector table, instead of flash 0x0000000.

            Then, the SPC ISR routine is in sram (file map), also the routine NonBlockingWriteRow is in sram (file map and check program counter reg. during debugging).

            In one (only one time) of my tests I was able to read CPUSS_SYSARG_REG to understand the cause of problem, or at least the cause in that test, it was 0xF0000012, from the manual:

            F0000012h Invalid Pump Clock Frequency - IMO must be set to 48 MHz and HF clock source to the IMO clock source before flash write/erase operations.

             

            I have seen that in this particular device CY8C4125AXI-S433, I can set IMO to 48MHz but it is not possible for HF (max 24MHz), could be this the problem?

            BR

            Renato

             

            • 3. Re: PSoC4100S SPCIF interrupt management to write flash row
              DheerajK_81

              Hello Renato,

               

              Yes you are right, looks like this register is not documented in the PSoC4100S Register TRM. But you can find it in the PSoC4 Register TRM.

               

              Here's the description of the bit of the CPUSS_CONFIG register.

              cpuss.PNG

              As you can see, when you set the bit to 1, it is going to locate the vector table in the SRAM.

               

              I have seen that in this particular device CY8C4125AXI-S433, I can set IMO to 48MHz but it is not possible for HF (max 24MHz), could be this the problem?

              I forgot to answer this question the first time. Yes, for the PSoC4100S device you need to set the IMO to 48MHz for flash operations. You can check which target devices need to do this in the Section 1.3 Target Overview of the PSoC4 Programming Spec.

               

              One thing I did observe is in the PSoC4100S Architecture TRM, Section 27.5.2 Configure Clock  seems to have its content missing. I will make sure this is fixed. Here is the table it seems to be missing.

              table.PNG

               

              Just add the System Call to configure the clock before performing any flash operations. It should now work.

               

              Let me know your observations. I will get the documentation fixed, sorry about the inconvenience caused.

               

              Regards,

              Dheeraj

              • 4. Re: PSoC4100S SPCIF interrupt management to write flash row
                ReMa_3807036

                Hi Dheeraj,

                thanks for your availability.

                 

                From documentation, I believe the CPUSS_CONFIG is not documented because it is substituted by VTOR reg, infact:

                In "PSoC 4 Architecture Technical Reference Manual (TRM)":

                6.3.3

                The vector table can be located anywhere in the memory map (flash or SRAM) by modifying the Vector Table Offset Register (VTOR). This register is part of the System Control Space of CM0+ located at 0xE000ED08. This register takes bits 31:8 of the vector table address; bits 7:0 are reserved. Therefore, the vector table address should be 256 bytes aligned.The advantage of moving the vector table to SRAM is that the exception handler addresses can be dynamically changed by modifying the SRAM vector table contents

                ....

                6.11 Exceptions – Initialization and Configuration This section covers the different steps involved in initializing and configuring exceptions in PSoC 4. 1. Configuring the Exception Vector Table Location: The first step in using exceptions is to configure the vector table location as required – either in flash memory or SRAM. This configuration is done by writing bits 31:28 of the VTOR register with the value of the flash or SRAM address at which the vector table will reside This register write is done as part of device initialization code.

                 

                 

                In any case I set CPUSS_CONFIG as you request and I check the value of VTOR reg, in the linked project that include your suggestion, really it is still not working.

                 

                As you can see in the project-example I have tried to set the clock IMO to 48Mhz, but the error code is

                "F000000Ch Key Opcode Mismatch – The opcode provided does not match key1 and key2"

                 

                It seems that the code "E8B6" are not correct for this micro...

                 

                If I comment that lines

                //while (value1 != 0xA0000000)

                //        value1 = CY_GET_REG32(CPUSS_SYSARG_REG_ADDR);

                 

                then after the command non blocking write "07 code", the error code is

                "F0000012h Invalid Pump Clock Frequency - IMO must be set to 48 MHz and HF clock source to the IMO clock source before flash write/erase operations."

                 

                Welcome your comment.

                Br

                Renato

                • 5. Re: PSoC4100S SPCIF interrupt management to write flash row
                  ReMa_3807036

                  Hi Dheeraj,

                  here the FW Archive05 with the right setting of IMO to 48MHz.

                  The problem was the setting of opcodes (0x0000E8B6) to be done by value to register CPUSS_SYSARG, not by pointer as in other cases (really the doc is not so clear about it).

                  ...

                  /**********************************************************************************

                      Set IMO to 48MHz

                  * Write key1, key2, byte address, and macro sel parameters to SRAM

                  *********************************************************************************** */

                  //REG( 0x20000A00 ) = 0x0000E8B6;  //WRONG MODE TO SET IMO to 48MHz

                  //CPUSS_SYSARG_REG = 0x20000A00;    //WRONG MODE TO SET IMO to 48MHz

                   

                  //Right mode is to write opcode directely to SYSARG   

                  REG( CPUSS_SYSARG_REG_ADDR) = 0x0000E8B6;      //PAY ATTENTION Load argument not the pointer

                   

                  //Write the API opcode = 0x15 to CPUSS_SYSREQ.COMMAND to setup IMO to 48MHz

                  // register and assert the sysreq bit

                  CPUSS_SYSREQ_REG = 0x80000015;

                  ...

                   

                  With the setting of IMO to 48MHz, the writing of flash is performed, and during that time (about 12ms in my check), it is possible to do other things (in the example there is a while loop with "DoOtherUserStuff()" for this scope).

                  Br

                  Renato

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