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In order for the Host PC to know if there is data available in the FX2LP, It should poll the endpoint through a subsequent read commands.
For an alternate way, you can implement a vendor command through the control end point whenever needed to check the availability of data in the endpoint buffer by monitoring the EPxCS ("x" is the EP number) register after the data is committed from the FIFO, and then perform a Read transfer from the host.
In either case, polling for availability of data is needed from the host side to FX2LP.
OK if i understand.
Today our FPGA and Firmware /Software implementation use ENDPOINT FIFO2 and 6.
FIFO6 to send command to FPGA from the HOST/PC.
FIFO2 to send DATA from the FPGA to the HOST/PC.
FIFO6 is an OUTPUT ENDPOINT.
FIFO2 is an INPUT ENDPOINT.
What you propose is to add for instance a new FIFO management.
FIFO4 for instance. As an INPUT ENDPOINT. The FPGA Fills this FIFO when needed (without any HOST request READ command).
A Specific Vendor Command need to be added in the Firmware. This specific vendor command, reads the EP4CS Empty or Full (depending of the management FPGA side) and Return a "there is DATA in the Buffer 4" information to the HOST/PC ?
Then the HOST/PC can read the FIFO4 ENDPOINT buffer ?
This is correct ?
That above solution which you have mentioned will work.
For a simpler way, you can directly check the Status of the EP2 (empty/not empty) which receives data from the FPGA, through the register EP2CS or EP2468STAT.
If the EP2 is not empty, then a read operation can be performed.
Also you can check the number of packets available in the FIFO by reading the NPAK bits of the EP2CS register.