8 Replies Latest reply on Jun 4, 2020 2:00 AM by MoPr_4537651

    PSoC 5LP SPI

    MoPr_4537651

      Hello,

       

      I wanted to interface a 20-bit SAR ADC to the PSoC 5LP. I realized that the SPI_master block only allows 16-bit data transfers at a time before the SS line goes back high. Is there anyway I can do a 20-bit transfer without the SS line going high at 16-bits?

        • 1. Re: PSoC 5LP SPI
          LePo_1062026

          MoPr,

           

          There was a similar discussion a while back:  SPI Master 3~16 bit width limit!

           

          I envision two choices to accomplish a 20bit SPI Master.

          1. Do not directly connect the SS line from the SPI Master component to your ADC.  Manually control the SS line in SW.  Configure the SPI Master as a 10bit transfer.  After two 10-bit transfers, toggle the SS line as needed.   Pro:  Fairly simple implementation:  Con: Since each 10bit transfer is done by SW, it's performance will be more limited.
          2. Create a new SPIM component with 20bit data length.  Pro: This can be done to create an efficient hardware state machine to maximize performance.  Con: Requires Verilog programming or extensive logic-gate creation in TopDesign.

           

          Len

           

          PS:  Would you share with us which 20-bit SAR ADC you are planning on using?

          • 2. Re: PSoC 5LP SPI
            LePo_1062026

            MoPr,

             

            Under most circumstances having more than a 16-bit SPI is not needed.  This is because the actual length of the SPI communications is delimited by one of two signals:

            • The chip select (CS) or slave select (SS) first going active then inactive after all the SPI bits are complete.
            • Occasionally the SPI device uses a D/Cn signal.  This signal is usually low (Cn active) during the Command phase and high (D active) during the Data phase.

             

            If you let me know which 20-bit SAR ADC you are planning on using I believe I can be more helpful.

             

            Len

            • 3. Re: PSoC 5LP SPI
              MoPr_4537651

              Hello,

              Sorry for the late reply. I am trying to interface AD4020 to the PSoC. Yeah I agree, I could do 2 10 bit transfers and control the ss signal in software. But like you said it has limitations on performance. I too feel that creation of 20 bit SPI is the better way, but I have no experience in verilog, so it is going to be very hard for me. What would you recommend?

               

              Like you mentioned, for AD4020 the CS signal stays high until conversion is done and it goes low until all the bits are transferred. And this cycle repeats for each time the ADC samples.

              • 4. Re: PSoC 5LP SPI
                LePo_1062026

                MoPr,

                 

                I downloaded the AD4020 datasheet from ADI.

                I can't say I fully understand the part but here's some suggestions:

                • Configure your PSoC5 SPI as a 8-bit data width.
                • The ADC uses a 16-bit SPI command.  When issuing commands, push 2 command bytes into the Tx FIFO.  Wait until SPI_Done to start the next SPI command.
                • Set the ADC to include the 6 bits of conversion status with the ADC conversion result.
                • The required tCONV is a max of 350ns with CNV (SPI_CS) going low before the SPI_CLK is started.   The PSoC5 SPI does place the SPI_CS before sending the SPI_CLK however depending on the input clock to the SPI component, this will vary.  One way is to control the CPI_CS (CNV) manually.
                • To receive the 26-bits (20-bits of data and 6-bit of status) put 4 'dummy' bytes in the Tx FIFO.  The extra 6 SPI_CLKs should be ignored by the AD4020 as long as SPI_CS (CNV) is still active low.  Once the 32bits of the converted data is retrieved, you can parse the results into ADC count data and determine if any status error conditions occurred such as OVERLOAD, etc.

                 

                To improve overall data conversion throughput, you can create a queue of SPI commands and data fetches.  Then you can either use the SPI_Done as an interrupt service routine to place the next queued command or data fetch into the 4 byte Tx FIFO.  Or ... You can carefully create a DMA TD-driven queue with data fetch result buffers to minimize the CPU overhead.

                • 5. Re: PSoC 5LP SPI
                  MoPr_4537651

                  LePo,

                   

                  There are several modes you can operate the AD4020 in. I'm only looking at the simplest mode (Shown below)

                  In this case, I don't have to send any data through SPI and I only have to receive 20 bits of data.

                   

                  I could do 2 10 bit transactions, but the only issue is the SS line in the PSoC will go high after every 10 bits right? Unless I manually control it. Ideally I want to do this without using the core. Any idea on how that can be done?

                  • 6. Re: PSoC 5LP SPI
                    LePo_1062026

                    MoPr,

                     

                    I could do 2 10 bit transactions, but the only issue is the SS line in the PSoC will go high after every 10 bits right? Unless I manually control it. Ideally I want to do this without using the core. Any idea on how that can be done?

                     

                    Actually no.  The SS line only deasserts (goes inactive high) if there is no further data in the Tx FIFO to send and the last Tx Data has left the shift register (ie. SPI_Done==TRUE).  The SS line remains asserted while the FIFO and shift reg has data to transfer.

                     

                    As I recommended in my previous post:

                    • Configure your PSoC5 SPI as a 8-bit data width.
                    • The ADC uses a 16-bit SPI command.  When issuing commands, push 2 command bytes into the Tx FIFO.  Wait until SPI_Done to start the next SPI command.

                    The SS line will remain active low until the 2 bytes of the command are sent.  Without placing more data in the Tx FIFO, wait for SPI_Done == True.  The SS line will automatically go inactive high.

                     

                    • Set the ADC to include the 6 bits of conversion status with the ADC conversion result.

                    Send  a command to the AD4020 is to include the 6-bit status with the 20-bit ADC result.

                     

                    • The required tCONV is a max of 350ns with CNV (SPI_CS) going low before the SPI_CLK is started.   The PSoC5 SPI does place the SPI_CS before sending the SPI_CLK however depending on the input clock to the SPI component, this will vary.  One way is to control the CPI_CS (CNV) manually.

                    If you don't want to control the SS line manually you will have to make sure the the required 350ns from SS going active to the first SPI_CLK is met by the SPI component.  You may have to lower the input clock to the SPI to guarantee this.

                     

                    • To receive the 26-bits (20-bits of data and 6-bit of status) put 4 'dummy' bytes in the Tx FIFO.  The extra 6 SPI_CLKs should be ignored by the AD4020 as long as SPI_CS (CNV) is still active low.  Once the 32bits of the converted data is retrieved, you can parse the results into ADC count data and determine if any status error conditions occurred such as OVERLOAD, etc.

                    The SS line will remain active low until the 4 bytes of the command are sent.  Without placing more data in the Tx FIFO, wait for SPI_Done == True.  The SS line will automatically go inactive high.

                     

                    Len

                    • 7. Re: PSoC 5LP SPI
                      MoPr_4537651

                      Ohh wow, that is awesome! Thanks for clarifying the behavior of SS I will try this in a few days and let you know

                      • 8. Re: PSoC 5LP SPI
                        MoPr_4537651

                        Hey, it seems to be working Will do more testing!. Thanks for your help