3 Replies Latest reply on May 22, 2020 6:29 PM by NiBu_4687336

    Cy_SCB_SPI_ReadArray documentation


      The documentation for the PDL function Cy_SCB_SPI_ReadArray() contains these two mutually-contradictory statements:


      • This function only reads data available in the RX FIFO. It does not initiate an SPI transfer.
      • When in the master mode, this function writes data into the TX FIFO and waits until the transfer is completed before reading data from the RX FIFO.


      Cy_SCB_SPI_Read() contains a similar contradiction.


      Is it safe simply to assume that the second statement is wrong?

        • 1. Re: Cy_SCB_SPI_ReadArray documentation



          The first point is valid when you are using the SPI block in slave configuration. The second point is valid for master mode. In master mode, the API works as a high level API that writes data/ dummy bytes to the slave, waits for the transfer to get completed and then reads the data from the RX FIFO.




          • 2. Re: Cy_SCB_SPI_ReadArray documentation

            Hi Apurva.


            Thanks for responding. Unfortunately, I'm now more confused than before. You say the so-labeled "low-level API" is actually a high-level API? This makes no sense to me.

            I've experimented by calling Cy_SCB_SPI_ReadArray() without first calling Cy_SCB_SPI_WriteArrayBlocking(), and no activity occurs on the SPI bus.

            Can  you tell me how I can use the SPI PDL to send data to a slave device and collect the data returned during that same transaction?

            Thanks again,



            • 3. Re: Cy_SCB_SPI_ReadArray documentation

              Hi Apurva.


              After thorough testing, I can say definitively that the PDL does NOT behave the way you suggested. Calling Cy_SCB_SPI_ReadArray() does nothing but read data from the SPI RX FIFO. It does not write to the TX FIFO. The documentation is, as I suspected, just wrong.