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Theoretically yes. In theory, a PSoC6 GPIO is effectively limited to 8mA source current. If you need to supply 10mA, I suggest you use at least two (preferably three) GPIO pins switched simultaneously to source >10mA.
Due to possible noise influence on the ADC and/or CapSense internal circuits, I recommend that these peripheral supply pins be switched when the ADC or Capsense is not needed or ignore the readings from these resources when you do switch.
Thanks. Will give it a try!
Are you willing to share which peripheral device you're using and the circuit connecting it?
The reason I ask is that sometimes controlling the power to the peripheral can get a little trickier than first thought.
For example, let's say you cut the power (VDD) to the peripheral but your comm signals from the PSoC use pull-ups (such as the SDA line for I2C). This pull-up could parasitically power your peripheral causing potential damage and at a minimum extra sleep current.
This is why many SPI and I2C comm peripherals have a hibernation mode. In this mode VDD is always applied but some signal (a serial command or a GPIO line) is used to place the device into hibernation.