How to measure small capacitors by switching ouput Pin’s drive mode + Timing measurement?

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AlCe_4092201
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Hi everyone,

I am trying to use PSoC 5LP to measure small capacitors (in the picoFarad range).

I'm not able to understand the reason why my code seems to be insensitive to the presence or not of a capacitor attached to the input pin P2.

Can anyone please help me to understand what's wrong with my code?

I think I did some mistakes in the way I changed the Drive Mode of the output pins P1, P3, P4 in the middle of the firmware, or maybe in the way I reset the Timer (to make it start counting in a precise instant inside the firmware).

I tried to exploit the Switching Capacitors algorithm illustrated in this Application Note from Microchip http://ww1.microchip.com/downloads/en/appnotes/01014a.pdf (in which a PIC microcontroller is used), to measure a small capacitance value Csen (22pF) by means of another capacitor Cint (of higher value, 10uF in this case) and eventually a resistor Rcal for calibration.

 

In order to apply this method I need to organize the firmware in different states and change dynamically the Drive Mode of the Digital Output Pins (from “Strong Drive” mode to “High Impedance” mode, and vice versa), while measuring the Time needed for the external capacitor Cint to charge up to an upper threshold VRH.

I used a Control Register to reset the Timer by firmware, and start measuring elapsed time) but the results are not even close to what I expected.

I tried to implement a state machine composed of 4 states, in which I changed the Drive Mode of output pins P1, P3, P4: 

(Pin P2 is always set as “High Impedance Analog”):

.state = DISCHARGE:                                     P1=0                     P3=0                     P4=0

.state = SWITCHING:

               (quick transition)                                       P1, P3, P4 = High Impedance

                ..substate= CHARGE                      P1 = 1                   P3=hi-Z                P4=hi-Z

  (quich transition)                                       P1, P3, P4 = High Impedance

               ..substate = SHARE                         P1 = hi-Z              P3=hi-Z                 P4=0

.state = CALIBRATION:                                 P1 = hi-Z              P3=0                    P4=0

.state = OUTPUT:                                           P1=0                     P3=0                    P4=0

Here attached is my PSoC creator file, consisting of 2 projects:

  • “SwitchedCapacitorTechnique”: this is the project in which I tried to replicate exactly the algorithm (except for the input pin parasitic capacitance Cpar, which I still need to evaluate) by using 4 different states: DISCHARGE, SWITCHING (consisting of 2 sub-states CHARGE and SHARE), CALIBRATION, OUTPUT.
  • “SwitchedCapacitorTec_SIMPLER” project which is a simpler version of the algorithm, in which I only implement 3 states: DISCHARGE, SWITCHING (charge+share), OUTPUT (thus ignoring the Calibration of Cint value). With this project, I obtain a value k1 = 28 (thus resulting in a C  sens = 415 nF instead of the 22pF I was expecting! And I obtain the same value even if I let Pin P2 as an open circuit, without any capacitor attached, thus there must be a HUGE mistake)

pastedImage_5.png

I am using:

  • CY8CKIT-059 PSoC5LP Prototyping Kit
  • Cint = 10 uF (external electrolitic capacitor)
  • Csen = 22 pF (external ceramic capacitor) – to be measured by this project
  • I consider Vdd = 5V since I am connecting the kit to my PC

During switching state:

  • VRH = 3440mV (upper threshold)
  • TSW = 5uSec (so the timer isr during switching state should occurr every 2.5usec)

During Calibration state: (not used in the “SwitchedCapacitorTec_SIMPLER” project)

VRL = 1250mV

TCLK = 0.5uF

Rcal = 2 kOhm (Pin P3 is NOT used in the “SwitchedCapacitorTec_SIMPLER” project)

Best Regards,

Alessia.

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1 Solution
Len_CONSULTRON
Level 9
Level 9
Beta tester 500 solutions authored 1000 replies posted

Alessia,

Measuring capacitance can be tricky even in the best of conditions.   When you are trying to measure capacitance in the pico-Farad range this is even more challenging.

You are correctly trying to consider input capacitance into the equation.  Another consideration is parasitic transmission line capacitance.

For example, if you are trying to use a multimeter with capacitance measurement try measuring a 1nF cap.  Not very stable is it?

If you're using a leaded 1nF cap, tape the cap to a table to stabilize the Cap-under-test.  Now move the meter wires.  Place the meter wires closer together.  You will notice the capacitance value goes up.  Place the meter wires farther apart, the measurement value should go down.

This is because there is parasitic capacitance between the '+' and '-' meter wires usually in the low pico-Farad range.

An additional factor that is difficult to compensate for is transmission line parasitic inductance.  The longer the fixturing wiring is, the more inductance that changes what was intended as a RC equation to an LRC equation.

When we are trying to measure low pico-Farad cap values where I work, we use specialized equipment from Wayne-Kerr that uses a calibrated fixture that factors out fixture/transmission line parasitics.

If you absolutely need to reasonably measure cap values in the pico-Farad range as a DIY project I would recommend the following:

  • Your test fixturing must be very stable and repeatable.  We have used custom PCBs where we solder the Cap-under-test (CUT) directly to the PCB.  This fixture becomes our CUT test points.
  • To calibrate your CUT fixturing leave the CUT test points open.  In this case, the capacitance of the CUT test points should be theoretically 0.  Your measured capacitance should be all the transmission line/fixture cap elements combined.  This capacitance measurement is used to 'zero-out' your fixture capacitance.  This is your cal NULL
  • If you solder the cap to the test PCB, make sure it is cooled down to room temp before the measure.
  • Measure your CUT and subtract the cal NULL.  The result should be close to the CUT value.  Note:  There will be ADC and Capsense circuit noise influences.  This will limit how accurate your measurement value will be.  Since the Capsense is a relaxation oscillator with a time-measured threshold crossing on the discharge, there are inaccuracies of the discharge resistor and the time reference (unless you are willing to invest in a XTAL source for the time-base).

In general the Capsense on the PSoC is intended to measure 'finger' present or not present signals.  It is more a binary threshold determination.    If you can arrange to achieve significant accuracy of capacitance measurement especially in the pico-Farad range, you should be applauded.  Either way, please share your experiences with the forum.  It may help others attempting to do something similar.

Len

Len
"Engineering is an Art. The Art of Compromise."

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6 Replies
Vasanth
Moderator
Moderator
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250 sign-ins 500 solutions authored First question asked

Hi Alessia,

These are the parasitic capacitance values you should be referring to.

pastedImage_0.png

Also there is a series resistance component introduced due to the routing of the input from the GPIO to comparator. The switch resitances will come into picture. Which can come around 1.1kohms when you run an ammeter in CYDWR -> Analog tab.

pastedImage_1.png

Then again the variation you are observing is not clear. Could you try saving the timer count immediately in the ISR and see if there is any difference in results ?

Best Regards,
Vasanth

Hi Vasanth,

Thank you for showing me where I can find the reference parasitic capacitance values and also the resistance of the analog routings inside the PSoC (I had no idea I could use the Ohm Meter inside the Analog Device Editor in order to estimate the R). This is a very useful tool.

At the beginning, I was supposed to save k1 value only at the very end of SHARE sub-cycle (both ISR_OVF and isr_comp_down events occurred), but since those nested if statements were giving me problems in the program flow, I decided to check for isr_comp_down occurrence separately ... 

Now I tried to save immediately the value of counter k1, as soon as the comparator event occurs (  isr_COMP_down ), and the results are different but not correct yet.

For example, with:      Cint = 100uF,      Csensed = 100nF:

Instead of:

     k1 =  34196

     Ar = 34*10^-6

     C_sen = 3 nF = 3406 pF

Now I obtain:

     k1 = 38885    

     Ar = 29*10^-6

     Csen = 2nF = 2995 pF

 

Also, k1 value is not stable/repeatable: it tends to increase everytime I reset the circuit (probably this is because I have still not implemented an accurate discharge at the beginning, I'm trying to fix it)

     k1 = 40193

     Ar = 28*10^-6

     C_sen = 2nF = 2897 pF

This is what outputs when Csen is not connected:

Previously:

     k1 = 41

     Ar = 28408*10^-6

     Csen = 2840 nF = 2840858 pF

Modified:

     k1 = 40

     Ar = 29118*10^-6

     C_sen = 2911 nF = 2911880 pF

Best regards,

Alessia.

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Len_CONSULTRON
Level 9
Level 9
Beta tester 500 solutions authored 1000 replies posted

Alessia,

Measuring capacitance can be tricky even in the best of conditions.   When you are trying to measure capacitance in the pico-Farad range this is even more challenging.

You are correctly trying to consider input capacitance into the equation.  Another consideration is parasitic transmission line capacitance.

For example, if you are trying to use a multimeter with capacitance measurement try measuring a 1nF cap.  Not very stable is it?

If you're using a leaded 1nF cap, tape the cap to a table to stabilize the Cap-under-test.  Now move the meter wires.  Place the meter wires closer together.  You will notice the capacitance value goes up.  Place the meter wires farther apart, the measurement value should go down.

This is because there is parasitic capacitance between the '+' and '-' meter wires usually in the low pico-Farad range.

An additional factor that is difficult to compensate for is transmission line parasitic inductance.  The longer the fixturing wiring is, the more inductance that changes what was intended as a RC equation to an LRC equation.

When we are trying to measure low pico-Farad cap values where I work, we use specialized equipment from Wayne-Kerr that uses a calibrated fixture that factors out fixture/transmission line parasitics.

If you absolutely need to reasonably measure cap values in the pico-Farad range as a DIY project I would recommend the following:

  • Your test fixturing must be very stable and repeatable.  We have used custom PCBs where we solder the Cap-under-test (CUT) directly to the PCB.  This fixture becomes our CUT test points.
  • To calibrate your CUT fixturing leave the CUT test points open.  In this case, the capacitance of the CUT test points should be theoretically 0.  Your measured capacitance should be all the transmission line/fixture cap elements combined.  This capacitance measurement is used to 'zero-out' your fixture capacitance.  This is your cal NULL
  • If you solder the cap to the test PCB, make sure it is cooled down to room temp before the measure.
  • Measure your CUT and subtract the cal NULL.  The result should be close to the CUT value.  Note:  There will be ADC and Capsense circuit noise influences.  This will limit how accurate your measurement value will be.  Since the Capsense is a relaxation oscillator with a time-measured threshold crossing on the discharge, there are inaccuracies of the discharge resistor and the time reference (unless you are willing to invest in a XTAL source for the time-base).

In general the Capsense on the PSoC is intended to measure 'finger' present or not present signals.  It is more a binary threshold determination.    If you can arrange to achieve significant accuracy of capacitance measurement especially in the pico-Farad range, you should be applauded.  Either way, please share your experiences with the forum.  It may help others attempting to do something similar.

Len

Len
"Engineering is an Art. The Art of Compromise."

Hi Len,

thank you for you advice, they are very useful as guidelines for this purpose.

I noticed it is more challenging that I thought. For the moment I am using a breadboard prototype, but still trying to fix the problem. I will share any results with the forum, of course.

best regards,

Alessia.

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odissey1
Level 9
Level 9
First comment on KBA 1000 replies posted 750 replies posted

Alessia,

There is Pins Annotation component, which helps to understand PSoC5 pins internals and pins configuration:

Pins Annotation component for PSoC5 and PSoC4

Particularly, you may be interested in 1-shot monostable example, which produces digital pulse by charging a capacitor. You can find description of the demo in the datasheet attached.

/odissey1

1-Shot Timer_01a_A.png

Alessia,

Following the Microcip's AN, this is how PSoC pins can be configured to realize switching capacitor technique. Note that instead of 4 pins only 2 PSoC pins are used, because Pin_1 has built-in comparator. To visualize the idea, the Pins Annotations are used instead of the actual pins, which should be sufficient to reproduce actual schematic. I did not test the project, this is just an idea.

SwitchingCap_01a_A.png

Pin_1 is configured for digital input and output, driving mode = OpenDrain, Drives High.

Pin_2 is configured for digital output, OpenDrain, Drives Low.

The measurement cycle is following

1. CReg_Start triggers PWM, which produces two anti-phase outputs with a dead band. When Csen is being charged, the Cint is disconnected.

2. The Pin_1 input (comparator out) will oscillate on each charging cycle until Cint is charged to a threshold level, and then stays High.

3. PWM is killed when both the Pin1 input and Pin_2 output are High (Cint reached the threshold, no need to charge any further), firing an interrupt (on Kill event).

4. Counter_1 counts total amount of PWM cycles between trigger and kill events, needed to charge Cint capacitor to the threshold level (CMOS).

5. When measurement cycle is completed the capacitors must be discharged. This can be done in software by setting Pin_1 to a Resistive Pull Down Mode, slowly discharging Cint thru Pin_1 pull-down resistor (~4.5k).

The threshold level can be set to other than CMOS (e.g. 1.024V) by using a SIO pin instead of GPIO (see Pins Annotation component datasheet for details). Lower threshold level improves linearity, shortens Cint discharge time and reduces discharge current.

Finally, please note that charging or discharging a large capacitor thru an open-drain pin can kill the pin due to overcurrent. I don't recommend attaching Csense larger than 10nF to an open-drain Pin_1. If any pin shows +5V on PSoC startup, that is indication that the pin is shorted.

/odissey1

SwitchingCap_01a_PWM_A.png