1 Reply Latest reply on May 10, 2020 9:58 PM by ApurvaS_36

    Issues with writing to the S25FL128L

    PhMa_4078046

      We are using the S25FL128L as a SPI FLASH PROM for our Lattice FPGA design. The PROM is being programmed from Lattice's tools using the indirect method. The programmer loads an image on the FPGA and that image passes data over JTAG to the PROM to write the bitstream. While the erases and writes to the PROM seem to complete we are noticing that the FLASH remains empty after the writes. The PROM appears erased (all FF's) after the writes. Here are some waveforms.

       

      At the start of the Lattice programming process, the programmer reads out the ID register. Note that it returns 0x19 as the last field in the ID. The datasheet for the S25FL128L states that 0x19 denotes a 256Mb device. We have checked the top-markings and the device is 128Mb.

      readID.png

      During the erases, we noticed that the Lattice programming process reads the status register. It's our understanding that if the Write-In-Progress (WIP) bit is zero after an erase or write that the erase or write succeeded. Looking at the erase, we see that is the case.

      erase.png

      Here is an example of a write:

       

      write.png

       

      Finally here is an example of a read:

      read.png

       

      We'd like to know if there are some possible reasons that a fresh PROM can behave in this way. Could issues on the bring-up of the power rails be a culprit? We'd like to know a few things we could try to figure out why we are seeing this issue.

        • 1. Re: Issues with writing to the S25FL128L
          ApurvaS_36

          Hi,

           

          Please answer my below questions -

           

          1. Could you please explain to me the reason for this delay in the last clock pulse marked in the waveforms below? This delay is present in the last clock pulse of the last byte in every transaction. Please go through the following article for clock frequency recommendations - SPI clock frequency for Cypress SPI NOR flash device – KBA226830 readID.png

          write_clk_delay.pngerase_clk_delay.png

           

           

          2. In the waveform for block erase (D8h) operation, I cannot see the CS# line being toggled after sending the write enable WREN (06h) command. Please see the marked waveform below -

          erase_cs#_toggle.png

          Please see the highlighted text from the S25FL128L datasheet below -

           

          3. Could you please explain to me what exactly are you trying to do in the write operation waveform? As per my understanding the command sequence in the waveform is 05h >> C0h >> 18h >> 01h >> 88h. As you already might be knowing, 05h is the RDSR1 command. Please tell me which command are you using for program operation and which is the address that you are trying to program? If possible, please provide another waveform for page program operation with command and address clearly marked.

           

           

          I would like to suggest you to do the following -

          • Kindly get rid of the delay in the clock pulses.
          • For erase and program operations, make the CS# line LOW, send the write enable WREN (06h) command and make the CS# line HIGH. Read Status Register 1 value at this point to make sure that the WEL bit has been set to 1. The SR1 value returned should be 02h.
          • If the SR1 value is 02h, try to perform the block erase and program operations again and let us know your observations for all the above operations.

           

          Best Regards

          Apurva