Please answer my below questions -
1. Could you please explain to me the reason for this delay in the last clock pulse marked in the waveforms below? This delay is present in the last clock pulse of the last byte in every transaction. Please go through the following article for clock frequency recommendations - SPI clock frequency for Cypress SPI NOR flash device – KBA226830
2. In the waveform for block erase (D8h) operation, I cannot see the CS# line being toggled after sending the write enable WREN (06h) command. Please see the marked waveform below -
Please see the highlighted text from the S25FL128L datasheet below -
3. Could you please explain to me what exactly are you trying to do in the write operation waveform? As per my understanding the command sequence in the waveform is 05h >> C0h >> 18h >> 01h >> 88h. As you already might be knowing, 05h is the RDSR1 command. Please tell me which command are you using for program operation and which is the address that you are trying to program? If possible, please provide another waveform for page program operation with command and address clearly marked.
I would like to suggest you to do the following -
- Kindly get rid of the delay in the clock pulses.
- For erase and program operations, make the CS# line LOW, send the write enable WREN (06h) command and make the CS# line HIGH. Read Status Register 1 value at this point to make sure that the WEL bit has been set to 1. The SR1 value returned should be 02h.
- If the SR1 value is 02h, try to perform the block erase and program operations again and let us know your observations for all the above operations.