1 2 Previous Next 20 Replies Latest reply on May 15, 2020 6:57 AM by LePo_1062026

    in psoc 5lp, how do you get the external clock signal into the systick counter?


      On page 1745 of the psoc 5lp registers TRM_001-82120.pdf, it is described that

      it is possible to get a DSI clock as the clock source for the systick.  bit 2,

      CM3_SYSTICK_SRCSEL  when set to "1" should use the signal connected to


      and a similar idea for the NMI source selection.


      my question is: how do i get a signal of my choice onto that signal name??

      i have read many community threads, documents and AN's, and tried various things

      in Creator and the output files to find this "dsi_01_out_p_13"

      signal, and have found nothing.

        • 1. Re: in psoc 5lp, how do you get the external clock signal into the systick counter?


          There is good tutorial how to use external clock as a system clock.

          External Clock

          The SysTick counter runs on the system clock (BUS_CLK), derived from the external clock


          • 2. Re: in psoc 5lp, how do you get the external clock signal into the systick counter?

            Thank you for the response.  but i do not follow if that is what i am looking for.

            i don't want to change the CPU clock: i still want that to run fast (66Mhz for example).

            so i am using an external Xtal, and the PLL is using Xtal as the source: and PLL

            sets the Master clock, and hence the Bus clock.


            SO, i guess the IMO is "free" to use for something else.

            i didn't want to use the IMO with Digital Signal input; unless that is the only way.


            More details:

            in the Psoc5 Ref Man.pdf, page 41, section 4.2.5 "SysTick Timer"

            says that the cortex-m3 register NVIC_SYSTICK_CTL selects whether

            the clock source is "internal" or "external".  and the second register (the PANTHER_WAITPIPE)

            which selects the "external" is the ILO or the DSI.

              so this makes it sound like there are 3 possible sources for this: and i want the DSI option

              (the ILO is not stable or accurate enough)


            And in that Configure System Clocks dialog, there is the yellow/green line going

            down from the Digital Signal item (you just cut it off in your picture).

            i was hoping THAT somehow could become this mystery "dsi_01_out_p_13" signal.


            by the way, how do i find this signal name?  where is it?  do i need a "Directive" to

            force it?  what is it?  (i am not an expert in the internal psoc naming and i don't find

            it in any clocking tree diagram)

            Same questions for the NMI signal as in the future i might want to use that also


            • 3. Re: in psoc 5lp, how do you get the external clock signal into the systick counter?

              I can change the clock source with a function CySysTickSetClockSource() and the interrupt period with a function CySysTickSetReload() as follows.


              #define SYSTICK_FREQ    (4)
              #define SYSTICK_CLOCK   (100000)


              In this case, the 100kHz ILO clock is used for the SysTick timer.  Please note that the 100kHz ILO must be enabled in the Clock Editor as follows.



              The callback function is registered by the CySysTickSetCallback() function.


                  /* Find unused callback slot and assign the callback. */
                  for (uint32 i = 0u; i < CY_SYS_SYST_NUM_OF_CALLBACKS; i++) {
                      if (CySysTickGetCallback(i) == NULL) {
                          /* Set callback */
                          CySysTickSetCallback(i, SysTickISRCallback);


              Please refer the "PSoC® Creator™ PSoC 3/PSoC 5LP System Reference Guide" which can be downloaded from a WEB page invoked by the following menu item.


              You can see SysTick related functions in the "System Timer (SysTick)" section.

              Please refer the example project "SysTick_Example" too.




              • 4. Re: in psoc 5lp, how do you get the external clock signal into the systick counter?

                Thank you for your response.

                I know how to and am using the ILO signal to drive SysTick.

                Your answer does not address my question of how to get the external DSI signal

                to clock systick.

                • 5. Re: in psoc 5lp, how do you get the external clock signal into the systick counter?


                  I am curious why do you want the SysTick timer to work from external source, when a standard Timer is available. Did you run out of all UDBs? Alternatively, the SysTick can work from ILO, controlled by 32kHz Quartz.


                  • 6. Re: in psoc 5lp, how do you get the external clock signal into the systick counter?

                    thank you for asking.

                    the psoc 5lp has a large "data size disconnect" between the 32bit wide CPU,

                    and the only 8 bit wide control/status register access to/from the logic.


                    suppose one wants to have a good, high speed 32-bit (or even wider counter), clocked

                    at say 4Mhz that is to be used as a time-stamper by the CPU.

                    Wouldn't it be great if the CPU could access this 32 bit value in a single instruction

                    cycle atomically?

                    You do see the massive problem if this counter is out in the logic: trying to access

                    a 32 bit value via multiple 8 bit status register reads? and then making sure the value was

                    read correctly?  and the extra effort to try and make the status registers align in memory

                    so one can try to use 16 or 32 bit pointer accesses? (i have a working solution for these

                    so i know them), but still have to then check for proper reading of the bit value?

                    or trying to do some DMA magic? (i have not tried this yet.  might have to...)


                    so using the logic takes a lot of cpu instructions: just to read a 32 bit counter !?!?!


                    the SysTick Counter is the ONLY counter i could find in the entire psoc 5 that is directly

                    tied into the CPU, readable with a single instruction, and with no apparent reading hazards.

                    Fantastic! a way to have a good, fast access, easy to use, reliable, Time Stamp generator.

                    well... almost.  accessing it is easy and works great: but it is clocked by awful clocks!!

                    the ILO is not accurate, unstable and slow!  the only other choice is the CPU clock:

                    with only 24 bits in the register: way tooo fast!


                    What !?!   this counter would be great!

                    if it only could be clocked by a real crystal controlled clock:  the type that are all over the digital logic!

                    and wow, there in the documentation says there is a way... if only one could figure out

                    that signal name... and i've spent some of yesterday and all of today trying to find anything about

                    that signal, or naming conventions on names or.... and have failed at everything.


                    That is why i want the systick counter to be clocked at say 200khz, 1Mhz, 2Mhz, whatever i choose.

                    and not the drifty ILO...

                    I hope you and/or the community can find the information and solve this for me and

                    all the others whose posts i've been reading for the past few days.


                    (i have tried your suggestion of driving the IMO with the DigitalSignal, and no, there is

                    no clocking of the systick.  so i still don't know how to attach to that magic signal )

                    • 7. Re: in psoc 5lp, how do you get the external clock signal into the systick counter?



                      While ago, there was a similar question, about how we can use DSI input for clock,

                      I tried to find the magic word for a half day and resigned.

                      But with this thread, now I know that the secret word was "ext_clk."


                      May be I'm missing something but with following wire name and clock configuration

                      I could provide external clock to PLL and generate 66MHz for CPU.




                      But as you wrote it seems that we have only 2 choices for the SysTick Clock source.


                      Then SysTick will be also clocked with the Matser_CLK = 66MHz.


                      But how about having upper bits counter counting with SysTick's TC?

                      Although as you wrote, accessing logic takes time, you get the lower 24 bits from the SysTick Counter

                      then hopefully accessing the upper bits will not take 16M (2^24) Cycles.


                      I know that this is clumsy, but may be better than nothing.



                      • 8. Re: in psoc 5lp, how do you get the external clock signal into the systick counter?


                        can you use a standard 32-bit Counter instead of SysTick? It will take 4 UDBs, but reading of the UDB is atomic.


                        Alternatively, you can use DWT timer of PSoC5, it is 32-bit (long enough even for BUS_CLK)

                        Measuring cycles using DTW on PSoC 6(M4)



                        • 9. Re: in psoc 5lp, how do you get the external clock signal into the systick counter?

                          Thank you for your response.  I am bypassing the as-provided C/h source code and looking

                          directly in the 5lp reference manuals, and thus directly can set/read the particular

                          register bits.  that way i am not hindered by the limits imposed by the C/h file writers.


                          some sort of "hybrid" between two different counters sounds harder to keep them

                          coherent than using the logic.

                          my prototype has been using the ILO to clock systick at 100khz;

                          and i use software to catch the wraparound and create a 64 bit coherent count.

                          and this has been working well enough for development.

                          and now i am back to trying to get a more stable clock rather than the ILO.

                          i had thought to use the watch crystal to make the slow speed clock: but i

                          think it is exactly the same problem: how to get a clock source of my choosing

                          to drive the systick.

                          • 10. Re: in psoc 5lp, how do you get the external clock signal into the systick counter?

                            BoTa, thank you for your response.  I've seen your work around this subject on the web

                            and i've made use of suggestions.

                            I still want to answer my original question of how to get a clock signal of my choosing

                            to drive systick.

                            (and i use software to maintain an in-cpu 64 bit coherent counter as systick overflows)


                            when i first was researching this (over a year ago) i did look at the WatchDog timer.

                            but rejected it as that is made to hard reset the chip; and i found no way to override that

                            so that is just to dangerous.  it would probably work fine in final product but would make

                            development and debugging a real pain.

                            thus i chose to use systick as harmless timing is what it is for.


                            as for a logic 32 bit counter.  that is what i have most recently worked out.  i followed some of

                            your work on the StatusReg32, and others (like the 32-bit parallel non-contiguous GPIO write technique )

                            and have that working.  i placed 4 status registers, forced their UDB locations such that their 8bit

                            access is in-address order and a single 32 bit pointer access works fine.

                            so the reading works.  however, the separate basic_counter whose outputs connect to these

                            status registers is the problem: signal skew, ripple count, delays all make the 32 bit value

                            NOT "coherent" when the fast cpu access happens: the CPU gets mixed up bits, non-linear

                            progression of the count.

                              (so i have the cpu read the count multiple times and compare them until stable over

                                the time needed for the HW to do a full clock of the HW 32 bit counter.  this takes multiple

                                instructions and if statements...)

                            and i have not found a way to have status registers "sticky" function

                            work for this as "sticky" is "clear on cpu read", which means a second cpu read will find

                            a 32 bit value of 0 !  until the next hw count increment clock comes in.

                            SO maybe using the counter32 counter with built-in status registers would do better

                            at keeping the count coherent, and still let me force the udb placement.

                            or insert a latch layer between my counter and the status registers; but even that

                            could still have a hazard because of differences in the clocks....

                            all this is sooo much effort (that some future maintainer of this would have to learn) that

                            i've not wanted to go there yet.... maybe later today i will do more experiments.


                            so i am still holding out the hope for systick...

                            • 11. Re: in psoc 5lp, how do you get the external clock signal into the systick counter?


                              did you see the modified 32-bit Counter?

                              Phase offset and Quadrature signal generator for lock-in

                              it is 32-bit, resides in the UDB Datapath, not PLD (as BasicCounter does), and works up to 80MHz BUS_CLK. The reading of the 32-bit Count should be atomic for Datapath (using CY_GET_RE32 (...)).


                              • 12. Re: in psoc 5lp, how do you get the external clock signal into the systick counter?



                                Sorry for being a late-comer to this melee of ideas from such a knowledgeable group of people.


                                As indicated eariler, the SysTick clock source can come from IMO and ILO and ILO_100 sources.  IMO clock source can come from the ECO XTAL or from a user defined input through the Digital Signal channel.  The external input can be a crystal based device external to the PSoC.


                                I realize legr_1685996 wants atomic coherency to the 32-bit counter value to have an accurate timestamp without 'hiccups' in the readings.


                                Here's my 'two-cents' (probably valued less than that).  Using the SysTick with an accurate clock input will yield a 24-bit coherent value.  Would that be enough bits at the least-significant (LS) part of your data?  If not, you need to clock faster to get more resolution.


                                If the problem is there is not enough bits in the most-significant (MS) part of the data,  you can use a SysTick interrupt to create a separate variable that increments the MS part of the data that adds to the lower 24-bits of the counter.


                                Consider this:  The SysTick counter value read in the LS part of your data is only as accurate at the time your CPU reads the counter.  Therefore there is latency from when the Event occurs requiring the timestamp:

                                • If the Event is tied to an interrupt:
                                  • Processing the interrupt.   (Assuming the interrupts are enabled and you're not already in another interrupt)
                                • If the Event is detected by polling a status:
                                  • Polling loop delays
                                • Reading the 24-bit SysTick value for the LS part.
                                • Adding any MS part to the LS part.


                                A very fast clock source to the SysTick will always be off a few counts at best by the time the SysTick counter read occurs.


                                Alternate suggestion:

                                If an uber accurate timestamp is needed with pin-point accuracy in the timestamp on the Event,  I suggest you use a UDB 32-bit counter with capture input.


                                If your Event can be boiled down to a single digital output, it can be used to feed a Capture input.  This Capture can occur on a rising, falling or both edge to capture the 32-bit timestamp value into 1 or 4 FIFO locations.  This is particularly useful if more than one Event can occur in short time proximity to another.  The latency I mentioned to determine the timestamp is virtually non-existent.   The Capture is HW determined and should have no coherency issues.


                                If the CPU is not fast enough to acquire 4 Event captures, a DMA channel can be allocated to grab the FIFO data and place them in a RAM buffer for latter analysis.


                                That's a lot of words for 'two-cents' but what the heck!



                                • 13. Re: in psoc 5lp, how do you get the external clock signal into the systick counter?

                                  Thank you Len (i am sure not that knowledgeable about psoc... yet)

                                  Yes, i use the 24 bits systick counter to feed a software maintained 64 bit counter.

                                  this is not interrupt driven; it is polled in a single-threaded way

                                  at semi-random times 10-30 times per second

                                  (when busy and the values matter, much more times per second when at "idle"

                                  and the values don't matter).

                                  i've used this idiom on other systems so i keep doing it the same way for consistency

                                  across these systems.

                                  the no-interrupt way means debugging is easy and no "critical sections" or locking

                                  is necessary.


                                  there is no hardware event associated with these time-grabs, so HW triggers and

                                  capture are not doable.  and Latency is not an issue here.


                                  one thing i was researching this morning is using a single datapath to maintain 24+ bits of

                                  count.  thus it would not be spread across multiple UDB's.  if a single datapath ALU

                                  could do that, and then have a DMA to move the result into CPU memory safe from

                                  access hazards only when the datapath signals it has a finished, coherent result,

                                  that would work well.  if these timestamps appeared in CPU memory with 1us granularity,

                                  that would be great (i can at this point tolerate 10us granularity).

                                  but i have never used the datapath.


                                  i have still to try BoTa's number 11: the modified 32 bit counter.  i tried the 32 bit counter

                                  approach almost 2 years ago, and it was very slow to read the count!  that was blindly

                                  using the normal API calls... long before i started researching further and doing

                                  direct register access type things.

                                  • 14. Re: in psoc 5lp, how do you get the external clock signal into the systick counter?

                                    Thank you BoTa: no i have not seen that.  i just got it, and am reading the downloaded info.

                                    i tried that component a couple of years ago, and it was very slow reading using the normal

                                    API calls.  i have not read/used the  CY_GET_RE32  call: is that a fast access thing?

                                    (i was going to try reaching inside the normal counter32 and Directive placement into

                                    memory address aligned status register locations... but have not had time yet today.


                                    i'm STILL holding out someone out there can find how to route the signal into the systick...

                                    i have a vague memory of long ago reading something about being able to look at the

                                    digital routing (not the analog: they have the editor for that) and see what the cross-point

                                    switches are and directly manipulating them....

                                    if i knew how to find that signal, on which logic block edge it was, and what switch(es) it

                                    connects to... then i could make headway....

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