I have a few questions regarding IDACs in PSoC 5LP CY8CKIT-059:
- In datasheet it's stated that the maximum DAC sample rate is 8 MSps and that the settling time to 0.5 LSB is 125 ns for 255 μA range for full scale transition, DACs running in fast mode and using 600 Ω 15-pF load.
- What happens if I strobe the DAC with frequency higher than 8 MHz? I assume that the DAC will work fine, but it won't be guaranteed that the output will settle to 0.5 LSB until DAC is strobed again. Is settling time for something like half scale transition lower than for full scale transition and is it affected by the load attached?
- How are DACs trimmed? I'm using 4 IDACs in source mode and would like to get the as close to ideal as possible, but it's even more important to get them as close to each other as possible.
- I found this question already answered in this thread, but it did not work for me:
A sample Calibration routine does the following:
The goal is to adjust the calibration code to get 256uA from the IDAC when the input code is 255 in the mid-range:
- Fix the digital input code to 255 and the calibration code to 128 (128 = 0b10000000 is the default value) and capture the DAC output.
- Determine the gain error.
- Apply the correct calibration code and capture the DAC output.
The default value of the Cal[7:0] is . Values lower than this will decrease the gain and values greater than this will increase it.
- When I increase the calibration code (for example 10000111) output current is decreased, but if I understood this correctly it should actually increase.
What am I doing wrong and what would be the best way to trim all 4 DACs to get them as close to each other as possible?
Is there any specific way that this measurement should be done? I tried connecting an ammeter directly between DAC output pins and ground and also through a 1k and 3.7k resistors, but it always behaves the same way.
This is an example of how I'm trimming the DACs in code:
IDAC_0_trim_val = 0b10000111; CY_SET_REG8(IDAC8_0_TR_PTR, IDAC_0_trim_val);
3. I've found a DAC Block Test Register in PSoc5LP_Registers_TRM, but I can't find any application notes or discussions about it. How does it work and how and when should it be used?
Any help would be appreciated.