7 Replies Latest reply on Jun 25, 2020 2:05 AM by VasanthR_91

    Question about PSoC 5LP IDACs (sample rate, trimming,...)

    user_3003661

      Hi,

       

      I have a few questions regarding IDACs in PSoC 5LP CY8CKIT-059:

      1. In datasheet it's stated that the maximum DAC sample rate is 8 MSps and that the settling time to 0.5 LSB is 125 ns for 255 μA range for full scale transition, DACs running in fast mode and using 600 Ω 15-pF load.
        • What happens if I strobe the DAC with frequency higher than 8 MHz? I assume that the DAC will work fine, but it won't be guaranteed that the output will settle to 0.5 LSB until DAC is strobed again. Is settling time for something like half scale transition lower than for full scale transition and is it affected by the load attached?
      2. How are DACs trimmed? I'm using 4 IDACs  in source mode and would like to get the as close to ideal as possible, but it's even more important to get them as close to each other as possible.
        • I found this question already answered in this thread, but it did not work for me:

      A sample Calibration routine does the following:

      The goal is to adjust the calibration code to get 256uA from the IDAC when the input code is 255 in the mid-range:

        • Fix the digital input code to 255 and the calibration code to 128 (128 = 0b10000000 is the default value) and capture the DAC output.
        • Determine the gain error.
        • Apply the correct calibration code and capture the DAC output.

       

      The default value of the Cal[7:0]  is [10000000]. Values lower than this will decrease the gain and values greater than this will increase it.

        • When I increase the calibration code (for example 10000111) output current is decreased, but if I understood this correctly it should actually increase.

                     What am I doing wrong and what would be the best way to trim all 4 DACs to get them as close to each other as possible?

                     Is there any specific way that this measurement should be done? I tried connecting an ammeter directly between DAC output pins and ground and also through a 1k and 3.7k resistors, but it always behaves the same way.

                     This is an example of how I'm trimming the DACs in code:

      IDAC_0_trim_val = 0b10000111;
      CY_SET_REG8(IDAC8_0_TR_PTR, IDAC_0_trim_val);
      
      

       

           3. I've found a DAC Block Test Register in PSoc5LP_Registers_TRM, but I can't find any application notes or discussions about it. How does it work and how and when should it be used?

      DAC_TST_reg.png

       

       

      Any help would be appreciated.

        • 1. Re: Question about PSoC 5LP IDACs (sample rate, trimming,...)
          BoTa_264741

          user_300..,

          What happens if I strobe the DAC with frequency higher than 8 MHz?

          PSoC5LP DAC has some issues operating at frequencies higher then (approx) 100kHz. There is a bit-flipping glitch, which occurs each 16 bits, resulting in a spike.

          Re: Filter-ADC-VDAC Sample & Hold

           

          This issue gets more pronounced with frequency, so that the DAQ becomes more like 7-bit, then 6-bit, etc... For example, PSoC4 DAC doesn't have this issue (at least not to this extent).

          I recommend to run a simple ramp test using a BasicCounter and IDAC8 with hardware bus enabled to observe this issue.

           

          How do you feed 4xIDAC with data at speed of 8 MHz each?

          /odissey1

          • 2. Re: Question about PSoC 5LP IDACs (sample rate, trimming,...)
            user_3003661

            Hi odissey1,

             

            DACs are used to convert sine wave samples from a LUT.

            I currently have multiple versions of the project I'm working on, and DAC bus and DAC strobing are controlled either by a component I have written in Verilog, or by another LUT. Looking at static timing analysis report, max clock frequency when running my custom digital component should be around 35.5 MHz, or even up to 161 MHz when using a LUT to control DAC strobing.

            Divided by 4 (since 4 DACs are used), this would give maximum sample rate of around 8.8 MSps to 40 MSps per DAC (in theory), so feeding the DACs is not an issue.

             

            Unfortunately I don't have an oscilloscope with me now, so these glitches are impossible for me to see right now. Are these glitches present only when running the DACs in their highest current mode, or do they appear in all modes? And could you further explain this:

            so that the DAQ becomes more like 7-bit, then 6-bit

            , I don't fully understand why would this happen.

             

             

            Also, does this happen only when turning xxxx1111<->xxxx0000?

            Take a look at the plot of expected DAC outputs and their combined output. DACs should practically be generating square waves of different amplitudes, so I don't know if this bit-flipping glitch would affect them in this case.

            dac_plot.png

             

            Thanks

            • 3. Re: Question about PSoC 5LP IDACs (sample rate, trimming,...)
              user_3003661

              Hi odissey1,

               

              I managed to get an oscilloscope and I saw the glitches you mentioned. They seem to be present for both 255uA and 2.04mA IDAC output current ranges.

               

              I measured these values using 460R resistor for the 2.04mA current range and 3.8k resistor for the 255uA current range to get similar voltage levels.

               

              The top screenshot is the DAC converting a full-scale ramp with current range set to 2.04mA and external 460R resistor, clock set to 4MHz.

              The lower is the same waveform, but now running with 255uA current range and external 3.8k resistor.

              SDS00001.png

              SDS00002.png

              Glitches are still visible in the signal when running with 255uA current range, but not nearly as much as when running with 2.04mA range.

               

               

               

              Below are the screenshots of a full-scale square wave, first with DAC set to 2.04mA current range and then to 255uA range with same resistor values as in the ramp example, with clock set to 1MHz.

              SDS00004.pngSDS00003.png

              Why is this overshoot happening? And why is it happening only when running the DAC in 2.04 mA range? These are both the same waveforms (full-scale square wave, 00000000<=>11111111). Is this connected to the output rise time (which increases with output impedance and should therefore be much lower for the 2.04mA range)?

               

              I'm wondering if there's a way to mitigate the effects of these glitches/overshoot, but only thing I can think of is to add an analog filter to the DAC output.

              • 4. Re: Question about PSoC 5LP IDACs (sample rate, trimming,...)
                user_3003661

                Hi,

                 

                It's been a while since the last post, but I've since found out that these massive overshoots do not happen when running the DACs in sink mode, even in the 2.04 mA current range.

                 

                Could anyone tell me what DAC architecture is used in PSoC 5LP (current steering?) and if there's an amplifier connected to the output or not.

                I only found this block diagram, but I would like to know a bit more about the architecture and the output stage (if it exists).

                dac_block_diag.PNG

                 

                The questions about DAC trimming, strobing the DACs at higher than max declared frequency and DAC Block Test Register are still open.

                 

                Any help would be appreciated.

                • 5. Re: Question about PSoC 5LP IDACs (sample rate, trimming,...)
                  VasanthR_91

                  Hi,

                   

                  In the DAC architecture there is no amplifier stage at the output. It is as shown in the image, there are multiple drive modes to be selected. It is connected to the output without any amplifier/buffer. When used as VDAC, the same output is connected to the  internal resistor without any buffer. That is the reason why load connected to the output should be capacitive. Otherwise any DC current drawn from the DAC affects the output level.

                   

                  Regarding the spikes, could you make sure that you are using the dedicated pins. The dedicated output pins are as following

                   

                  The IDAC is connected to the GPIO through the analog trace. So the trace inductance and capacitor of internal analog trace and external trace causes the sudden glitch when the IDAC is switched. Using the dedicated pins reduced the trace resistance. Additionally you can connect the load capacitor at the output of IDAC along with resistor.

                   

                  DAC block trim registers are used for trimming the DAC component, not the DAC block test registers.

                  There are 8-bits of calibration available to correct upto +/-25% of gain error. DAC Block Test Register are not expected to be used by user for this purpose.

                   

                  Best Regards,

                  Vasanth

                  • 6. Re: Question about PSoC 5LP IDACs (sample rate, trimming,...)
                    user_3003661

                    Hi Vasanth,

                     

                    Yes, I'm always using one of the dedicated pins (P0[6], P0[7], P3[0], P3[1]) when running the DACs in the 2 mA current range.

                     

                    Here is a scope screenshot of the same full-scale transition with one DAC running in sink mode (CH1) and the other in source mode (CH3). As you can see, this massive overshoot happens only with the DAC running in source mode. Both DACs are set to 2.04 mA current range and are connected to VDD/GND with resistors of the same value.

                    2mA_820R_500kHzClk.png

                     

                     

                    Regarding the DAC trimming, I already tried setting DAC_trim value, as I mentioned in the original post. When I increase the calibration code (for example 10000111) output current is decreased, but if I understood this correctly it should actually increase. I thought that maybe MSB and LSB are reversed, but as far as I can see that's not the case.

                    This is an example of how I'm trimming the DACs in code:

                    IDAC_0_trim_val = 0b10000111;

                    CY_SET_REG8(IDAC8_0_TR_PTR, IDAC_0_trim_val);

                    • 7. Re: Question about PSoC 5LP IDACs (sample rate, trimming,...)
                      VasanthR_91

                      Hi Tomislav,

                       

                      Yes, your understanding is right. The change in the callibration regiser to the current is in opposite direction. I will correct the mistake in the mentioned thread.

                       

                      Now regarding your requirement, :

                      What would be the best way to trim all 4 DACs to get them as close to each other as possible?

                      You may use the internal comparator and routing/Mux to TRIM all the comparator to the required accuracy. The DAC's can be set with value corresponding to Vref (1.024 V). Then the measurement can be contined till the tripping point of the comparaor to fine-tune every IDAC. The external resistor accuracy, comparator offset, Vref offset and routing resistances affect the final result though.

                       

                       

                      Best Regards,
                      Vasanth