Hardware Required - CY8CKIT-145-40XX development kit with PSoC 4000S chip, Oscilloscope for testing
Software Required - PSoC Creator 4.2
Summary - This project shows a simple approach on how to obtain a delayed signal using SmartIO component in PSoC4. In this project, LUT of SmartIO is used to buffer the signal.
I tested this project on CY8CKIT-145-40XX development kit which has PSoC 4000S micro-controller on it. The LUT is configured in Registered output mode. SmartIO input is Synchronous. I have used a PWM to generate input signal. I have configured the PWM to generate a square wave of 10kHz frequency so that clock frequency of SmartIO is considerably higher compared to input frequency (SmartIO clock frequency is 5MHz). One important parameter we should know for this implementation is the maximum frequency of input signal. We can not buffer an input signal with higher frequency than the clock given to SmartIO.
I have attached PSoC Creator project. Also, I have attached a screenshot of testing on Oscilloscope. In the image, blue line indicates input of SmartIO and yellow line indicates the output signal. It can be observed that output is delayed by 500ns compared to input signal.
Question - The delay observed between input signal and output signal is 500ns. As per LUT configuration, signal is buffered by one clock cycle. Input clock for SmartIO component is 5MHz. So, I expect a delay of (200ns + some small additional delay due to signal propagation) between input and output signal. Why do I see 500ns delay between input and output signal in this case, which is more than double of one clock period? Can anyone help me understand this?
The Input signal from the PWM passes through a double synchronizer and this introduces up to a two cycle delay to the input signal. This is done when you choose Input (Sync) option in the configurator.
Hope this explains the result you are observing.