5 Replies Latest reply on Jun 3, 2020 10:50 PM by DheerajK_81

    PSoC 6 Dual Core Debugging


      Is there a guide to Dual Core Debugging for the PSOC 6 within Keil uVision?


      Specifically, customer needs to be debugging the CM4 and when a breakpoint is hit on the CM4, he would like the CM0+ to stop as well.


      I think there are bits that need to be set for the CTI and CTM, but we cannot find the documentation on how this is done.