5 Replies Latest reply on Apr 28, 2020 7:12 AM by AlTo_2058231

    Top Design PWM limiter

    AlTo_2058231

      Hello there,

       

      I'm personally quite new in the PSoC world, but my company develops on this chips since PSoC 3 release.

      We are aiming to switch to the PSoC 6 in the future and I'm studying for products design improvements.

      There are so many changes that we'll a lot of work to do, but I'm here now to ask you a thing that might be backported also to PSoC 3.

       

      At the moment we are using a PSoC 3 to control a brushed 24VDC motor through a PWM signal over an external H-bridge driver.

      So we modulate the PWM to get a proper motor velocity and we close a control loop over an encoder to get precise positiong.

      Since we have an external load that can change impulsively, we have implemented a software current limiter inside the PSoC code, to avoid motor faults when exceeding the maximum nominal and peak currents of the DC motor. This is done basically by limiting the PWM max value when the measured current is above the given threshold.

       

      Since the PWM block is inside the Top Design alongside the Del-Sig ADC for current measurement, I was wondering if it could be possible to move also this software limiter (or something similar) inside the Top Design. This should help to get rid of the potential delays during software computation (we have other routines that cycles on the PSoC, including communication interrupts handling).

      Also, I think that moving it to the Top Design would improve the current limiter dynamics, which is sometimes much slower w.r.t. the impulse.

       

      Do you think that it is feasible?

      And what about performance improvements?

       

      Thank you very much for your help

      Alessandro

        • 1. Re: Top Design PWM limiter
          GaneshD_41

          Hi Alessandro,

           

          We recommend you to check with PSoC 4 instead of PSoC 6.

           

          In PSoC 4 there is a digital peripheral called UDB which you might be aware of. You can design custom digital component/glue logic/state machine uisng the UDB components in PSoC 4.

           

          Your requirement seems to be possible using UDBs in PSoC 4. But it also depends on the type and how big the size of logic that you are implementing. The UDBs present inside the PSoC may or may not be suficient to implement the software logic that you presently have. We recommend you to check with PSoC 4L device family.

           

          Please check the attached documentation which provides documents related to UDB.

           

          Also, we recommend you to look at a new product from Cypress (link given below) which provides 2 Motor Control Accelerator blocks. Please note that for this particular product, there are no UDB blocks available. The tentative release of this product is by the end of this month.

           

          https://www.cypress.com/file/495441/download

           

          Thanks

          Ganesh

          • 2. Re: Top Design PWM limiter
            BoTa_264741

            AlTo,

            I believe that the problem is artificial. During the overload conditions, the PWM duty cycle comes from the PSoC C-code, so it simply should be limited in the code before applying it to the PWM.

            /odissey1

            • 3. Re: Top Design PWM limiter
              AlTo_2058231

              Thanks GaneshD_41 for all the info on UDBs that I was aware but I have not yet dig deeper into them.

              I've studied a bit of Verilog during my bacelor's degree, but it might be hard for me to pursuit that way.

               

              However I was not aware that PSoC 6 does not provide UDBs, does it?

              The choice of PSoC 6 is not yet definitive for us, but there are many other reasons to make the switch with it, and I'm sorry that the question I asked was instead a bit unrelated and more general to the whole PSoC world.

               

              I was wondering something more like using a simple logic with the already present blocks (comparators, ADC, DAC, ...) to implement a simple PWM limiter, but I think that is not that easy (or even feasible, as said by BoTa_264741) by using only the official blocks.

               

              Maybe a custom UDB block that implements a custom PWM generator and also includes the current check could be a choice, but I think I'm not skilled enough for that.

               

              Anyway, thanks to both of you!

              • 4. Re: Top Design PWM limiter
                LePo_1062026

                AlTo,

                 

                Some PSoC6s have UDBs others do not.

                 

                For those PSoC6 that have UDBs, they can only be programmed in Creator at this time.  ModusToolbox does not support UDBs.

                 

                Len

                • 5. Re: Top Design PWM limiter
                  AlTo_2058231

                  Thanks for the clarification LePo_1062026.