7 Replies Latest reply on May 5, 2020 12:05 AM by ApurvaS_36

    s29gl512p.sv model


      The SystemVerilog simulation model for the S29GL512P part (512Mbit x8/x16 Page mode Flash Memory) has the following 2 issues:


      1- In the absence of protected sector, the memory write and sector-erase operations are not working.


      The reason for this is that the following variable declaration defaults to a value of 'X:

          integer  ProtSecNum;

      And so every comparison with this variable needs to use the 4-state equality operator (===) as opposed to the 2-state (==) operator.



      2- There's a considerable simulation slow-down as more memory addresses are being accessed.


      Replacing the linked list implementation by an associative array construct from SystemVerilog solves the issue:

      rw_interface_c rw_interface;

      int mem_assoc_arr[int];  // data integers are stored, where the key (address) is an int

      Of course, the read_mem_w(), write_mem_w() and erase_mem_w() tasks had to be updated to make use of the new associative array variable.