1 Reply Latest reply on Apr 24, 2020 3:11 AM by RashiV_61

    cx3 Image sensor configuration qustion

    gyle_4646071

      Did I set the values correctly?

      1280 * 720 @30fps , 4lane, RAW12

       

      CSI clock  : 448Mhz

      Data Lane : 4 LANE

      THS-Prepare : 70

      THS-Zero : 170

      Frame rate : 30fps

      H-Active : 1280

      H-Blanking : 1256

      V-Active : 720

      V-Blanking : 16

      Data format : RAW12

       

      1. Can csi clock be over 400Mhz at 4 lane?

       

      2. CX3 MIPI Reciver Configuration default value is O.K?

       

      /* null_RAW12_Resolution0 :  */

      CyU3PMipicsiCfg_t null_RAW12_Resolution0 = 

      {

          CY_U3P_CSI_DF_RAW12,  /* CyU3PMipicsiDataFormat_t dataFormat */

          4,                          /* uint8_t numDataLanes */

          2,                /* uint8_t pllPrd */

          89,            /* uint16_t pllFbd */

          CY_U3P_CSI_PLL_FRS_250_500M, /* CyU3PMipicsiPllClkFrs_t pllFrs */ 

          CY_U3P_CSI_PLL_CLK_DIV_4,    /* CyU3PMipicsiPllClkDiv_t csiRxClkDiv */

          CY_U3P_CSI_PLL_CLK_DIV_4,    /* CyU3PMipicsiPllClkDiv_t parClkDiv */

          0,                        /* uint16_t mClkCtl */

          CY_U3P_CSI_PLL_CLK_DIV_2,    /* CyU3PMipicsiPllClkDiv_t mClkRefDiv */

          1280,                /* uint16_t hResolution */

          50                            /* uint16_t fifoDelay */

      };

       

      3. Are there any more settings I need to add?

       

       

      Best regards.

        • 1. Re: cx3 Image sensor configuration qustion
          RashiV_61

          Hello,

           

          1)Can csi clock be over 400Mhz at 4 lane?

          >>  The maximum bandwidth that CX3 can support is limited by the GPIF II block of CX3. As mentioned in TRM it can support till 2.4Gbps i.e. when 100 MHz clock and 24 bit GPIF interface is used. So if you want to use all the 4 lanes, then CX3 can support only 600Mbps/lane. Else the video will not stream properly due to data loss.

           

          As CSI clock is DDR clock you can keep the CSI clock less than 300 MHz when you are using all 4 lanes and GPIF interface is of 24 bits. If GPIF interface is of 16 bits the bandwidth will reduces further and hence need to reduce the CSI clock further.

           

          2) CX3 MIPI Reciver Configuration default value is O.K

          >> Other than the CSI clock everything else seems fine. You can modify the clock and share the settings, once again, for us to check.

           

          3) Are there any more settings I need to add?

          >> No additional settings are needed for CX3 MIPI Receiver Configuration.

           

          Regards,

          Rashi