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Dear Readers,
In DmaMultiChannelConfiguration it is possible to have two producer PIB socket and CY_U3P_CPU_SOCKET_CONS as consumer socket.
when we are trying the above configuration, we are getting configuration error.
but when i tried UIB socket as consumer socket it is working fine
Solved! Go to Solution.
- Tags:
- fx3
- multichanneldma
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Hello,
For a DmaMultiChannelConfiguration, it is not possible to have the CPU socket as a Producer or consumer. The only possible Producer and consumers for DmaMultiChannelConfiguration are : UIB, SIB, PIB and the LPP Blocks. If CPU socket is used as a producer or consumer in DmaMultiChannelConfiguration, then the API CyU3PDmaMultiChannelCreate will return error code 64 (0x40) indicating Bad Argument.
Best Regards,
Jayakrishna
Jayakrishna
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Hello,
For a DmaMultiChannelConfiguration, it is not possible to have the CPU socket as a Producer or consumer. The only possible Producer and consumers for DmaMultiChannelConfiguration are : UIB, SIB, PIB and the LPP Blocks. If CPU socket is used as a producer or consumer in DmaMultiChannelConfiguration, then the API CyU3PDmaMultiChannelCreate will return error code 64 (0x40) indicating Bad Argument.
Best Regards,
Jayakrishna
Jayakrishna
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Hi Jayakrishna,
I have taken UVC (AN75779) as a reference design. in which I have changed the UVC descriptor to USB descriptor (0X83 IN Endpoint) and Using the same GPIF interface.
FPGA is connected to the FX3 through the GPIF interface. From FPGA I am sending counter data 2712 bytes/line and 10848 bytes/frame to the FX3 at 40MHZ speed.
when I am reading the data from the host, I am getting backflow error and DMA commit error because of that I am getting loss of some frame and some data less than the actual frame size(less than 10848).
Please suggest what can I try to resolve the DMA commit and backflow error.
Thanks
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Hello,
The discussion for your question in response 2 can be done in the following thread:
commit error and back flow error in UVC AN75779
Best Regards,
Jayakrishna
Jayakrishna