Try the following steps:
- Open the DWR (Design Wide Resources)
- Select the Clock Tab.
- Find the Clk_Peri and check the Nominal Frequency. It's probably set to 50MHz. You want 100MHz.
- Check if the Clk_Peri Divider value = 2. If true, you want to change it to 1.
- if 4. is true, select Edit Clock.
- Change the Divider: field in the Clk_Peri to 1.
- Select OK.
- You should now see that back on the DWR/Clock/Clk_Peri/Divider should now indicate 1 and the Nominal Frequency = 100MHz.
Note: All other components/peripherals being driven from the Clk_Peri clock may need to be adjusted. Some components will auto-adjust to the new driving clock (such as the UART), others may have to be manually adjusted.
Give it a try.
Thank you for your help. I've already done these steps. My Clk_Peri is 100MHz
But when I connect a 100MHz clock (Clk_Peri / 1) to a UDB component (lets say a DFF for this example) as shown below
I get the following error:
I need to use 100MHz clock in my digital design but I can't. I have tried both a verilog implementation or an only datapath implementation.
1 of 1 people found this helpful
Indeed the circuits are equivalent. I was just trying to reproduce the error as simple as possible. I needed the registers to get the design to be actually synthesized. Maybe you can get rid of the status register and connect a GPIO instead.
So with your help, I noticed what was wrong with my setup.
Apparently you can't use Clk_Peri / 1 like this:
But you can use Clk_Peri directly instead:
Thank you for your help!