1 Reply Latest reply on Apr 21, 2020 5:40 PM by RodolfoG_11

    Verilog floor planning/timing question

    DaHa_1249911

      So I'm working on a system in which I've got a PSoC 6 as an I/O and management processor and a small x86 as the main processor. Rev 1 is in house and mostly working, and I'm working on revisions.

       

      The software team is interested in a faster, super low level interface for debugging, and we couldn't think of anything lower level than using the IO Port instructions and the LPC bus, so I set forth building an LPC bus interface into the existing design, which has a bunch of other logic, peripherals, etc.

       

      I was close, but couldn't quite nail the 25MHz performance necessary, at least according the timing analyzer. I set every pin to its appropriate speed class (hoping that prioritizes floor planning), unlocked everything, and bingo! It's all rompin' along with some margin. I lock down the automatically selected (and presumably optimized) pins for the LPC interface, proceed to enter in the existing pinout, much as possible. Press "go!" and not I'm back down below 25MHz.

       

      This seems a little random. Isn't there a way to lock down what works and let the Creator basically route everything around that, or fail and make me move pins. I'm trying to minimally affect the exising very tight PCB layout, and there doesn't seem to be any way other than many hours of trial and error, routing the rest of the design. Or simply biting the bullet and trying to fit the newly allocated pinout.

        • 1. Re: Verilog floor planning/timing question
          RodolfoG_11

          Once you find a placement that works for you, you can lock it using the Design Wide Resources > Directives.

          Add a directive and choose Force Component UDB.

          The signal names and UDB location are in the RPT file. In the Workspace Explorer > Results Tab.

          In the RPT file, search for the name of the UDB component you created.

          For example, a control register (Control_Reg_1) might show like this:

          UDB [UDB=(1,5)] contents:

          controlcell: Name =\Control_Reg_1:Sync:ctrl_reg\

           

          If that's the case, add a directive like this:

          Component (Signal) Name: \Control_Reg_1:Sync:ctrl_reg\

          Directive Type: ForceComponentUDB

          Directive Value: U(1,5)