1 Reply Latest reply on Apr 21, 2020 12:33 AM by NoriakiT_91

    problems with I2C CY8CMBRS108



      I have some problems with the I2C Communication. I try to implement a communication between µC and CapSense IC. The I2C SCL clock frequency is initialized at 100kHz and current the µC waits 2s before it starts the communication. Also I try 350ms or 1s or 15ms or 915ms(T_I2CBoot and TBOOT_SYS). But always the CapSense IC sends NACK.

        • 1. Re: problems with I2C CY8CMBRS108

          I am assuming you are talking about CY8CMBR3108 (MBR3).


          MBR3 chips has deep-sleep mode to reduce the power consumption. The I2C communication is used to wake-up the MBR3 chip and MBR3 chip returns a NACK to the I2C communication.




          It is described in the datasheet as follows.

          The CY8CMBR3xxx controller is expected to NACK the address match event if it is in the low-power state (during any of the operational states – Deep Sleep, Look-for-Touch, Look-for-Proximity, or Active). The controller wakes up from the low-power state on an address match but sends NACK until it transitions into the Active state and, on for the first transaction, in the active state. When the device NACKs a transaction the host is expected to retry the transaction until it receives an ACK.

          So, please try to send a dummy I2C transaction to wake-up the MBR3 chip, then send READ and/or WRITE I2C packets.




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