2 Replies Latest reply on Apr 20, 2020 12:05 AM by chwa_1570756

    Can I disable all of FIFO and buffer in SPI port?

    chwa_1570756

      Hello,

       

      I make a motor control system, need very fast communication on SPI interface, I want to disable all of internal TX/RX buffer or FIFO,

      there are only two shift registers left, one in master one in slave, then I can get a simple fast data exchange loop.

      I can find the command of SPIS_WriteTxDataZero, which can write data into shift register well.

      So, why there are no command like, SPIS_ReadRxDataZero, SPIM_WriteTxDataZero, SPIM_ReadRxDataZero ?

       

      thanks.

      Chris

        • 1. Re: Can I disable all of FIFO and buffer in SPI port?
          NoriakiT_91

          Chris,

           

          SPIS_WriteTxDataZero writes a txDataByte to the SPIS_TXDATA_ZERO_PTR which is the shift register.

           

              void SPIS_WriteTxDataZero(uint8 txDataByte)
                                                  
              {
                  CY_SET_REG8(SPIS_TXDATA_ZERO_PTR, txDataByte);
              }
          

           

          On the other hand, SPIS_WriteTxData writes a txData to the SPIS_TXDATA_PTR which is the input port of the hardware FIFO connected to the shift register.  Because this function uses FIFO, the status of FIFO must be monitored prior to the write operation.

           

                  /* Wait until TX FIFO has a place */
                  while(0u == (SPIS_TX_STATUS_REG & SPIS_STS_TX_FIFO_NOT_FULL))
                  {
                  }
          
          
                  /* Put data element into the TX FIFO */
                  CY_SET_REG8(SPIS_TXDATA_PTR, txData);
          

           

          As of SPIS_ReadRxDataZero and SPIM_ReadRxDataZero, the data received to the shift register is automatically transferred to a FIFO.  So, you don't need to access to the shift register directly.  You can access to the data via FIFO.

           

          As of SPIM_WriteTxDataZero,  SPI master must start a transfer when a new data is written to the shift register.  The FIFO is required to create the timing to start a transfer.

           

          In addition, you can use a DMA on SCB based SPI to access to the shift register via FIFO to reduce the overhead by accessing  them using a software.

           

          Regards,

          Noriaki

          • 2. Re: Can I disable all of FIFO and buffer in SPI port?
            chwa_1570756

            Hi Noriaki,

             

            You remind me the DMA operation way to access hardware directly.

             

            Thanks