Please find our comments below.
1) There is no significant architectural difference between the 4Mb and 2Mb parts.
2) The exposed pad on CY15B104Q-LHXI should not be soldered. Soldering the exposed pad will expose the F-RAM die to excessive heat, which may result in bit failures and margin loss. Hence it should be left floating without connecting to any pad on the PCB. Even the datasheet for FM25V20A recommends to not solder the exposed pad. Can you check for failure on another device without soldering the exposed pad?
3) The issue mentioned in App note 302 is no longer applicable for FRAM parts as the parts with these issue were obsoleted and no longer available. The app note was anyways not applicable for CY15B104Q.
Fixing the issue should resolve your issue, if you have any further concerns you can let us know.
Thanks and Regards,
Thanks for your reply, much appreciated. We’ll try some experiments to see if this fixes the problem.
Just trying to understand the issue further, am I right in saying that the device can get damaged during the soldering process? We use vapour-phase soldering, where the whole device should get to an even temperature – are there any restrictions on using vapour-phase reflow for this device?
Also, if the problem is purely to do with heat damaging the device, am I right in saying that there are no electrical effects of connecting the central pad? Our PCB footprint has a corresponding pad I’m wondering if removing the solder paste from the pad before reflow would be an acceptable solution. This way, there will be no soldered connection and therefore less heat transfer, but there will still be an electrical connection. Is this acceptable?
I guess I’m wondering about the purpose of the pad on the device.
Thanks again for your help,
Please find my comments below.
The purpose of the pad on the device is that Standard QFN or DFN package has always been with exposed pad for thermal performance. If it was design without exposed pad, it would be a custom leadframe/package. We do not want to offer a custom QFN/DFN package with unproven manufacturability and reliability. So we have a DFN package with note says that EXPOSED PAD should not be soldered.
Our QTP (qualification) data is based on the use of convection solder reflow ovens (and not vapor phase solder reflow ovens). So unfortunately, we don’t have any data to answer your question on this.
DO NOT Design any land pattern on the PCB (Definition of the package in the library) -> the stencil will have no "window", no solder paste will be present -> no soldering of the exposed PAD to the PBA at all -> no risk of contact to any land pattern.