5 Replies Latest reply on May 6, 2020 11:37 PM by PradiptaB_11

    Minimal Sram frequency

    GIGR_4685016

      Hi,

      I'm using CY7C1618KV18 DDR II device.

      The minimal clock frequency is defined in the datasheet to 119Mhz (K & C max clock cycle time = 8.4ns).

      Is it safe to use slower clock frequency, e.g 80Mhz?  What is the lowest supported frequency?

      Thanks,

       

      Gil

        • 1. Re: Minimal Sram frequency
          PradiptaB_11

          Hi Gil,

           

          When you operate the DDR II device at frequecies below 120 MHz the PLL has to be disabled by tying DOFF# to GND. PLL is bypassed by strapping the DOFF #  signal LOW. In this mode, the read latency for QDR-II/II+/DDR-II/II+ devices is 1.0 clock cycle and the timings are
          guaranteed by design but not tested.

           

          So to answer your question it is safe to operate at slow clock frequency. There is as such no limit to lowest supported frequency, as it is not a tested parameter. Hence i cannot provide you a fixed number for this.

           

          Thanks,

          Pradipta.

          • 2. Re: Minimal Sram frequency
            GIGR_4685016

            Hi Pradipta,

            Thanks for your answer.

            More questions:

            1. The SRAM datasheet specifies max freq. of 167Mhz and DDR I timing when DOFF=1.

                Does DDR I timing differs from DDR II except for 1 vs. 1.5 clock cycles read latency?

            2. Can I change DOFF value during operation, or only at power-up?

             

            Thanks,

              Gil

            • 3. Re: Minimal Sram frequency
              PradiptaB_11

              Hi Gil,

               

              Please find my comments below.

               

              1) The read latency is different and also the access time will be longer when the PLL is turned off.

               

              2) The DOFF# value is recommended to be applied during power up. If you change the value at any other time it may lead to some undefined operations.

               

              Thanks,

              Pradipta.

              • 4. Re: Minimal Sram frequency
                GIGR_4685016

                Hi Pradipta,

                Thanks for your answer.

                1. Do you have a dataheet that describes the access time and other timing parameters when DOFF# = 0 ?

                2. Do you have a behavioral model for simulation that supports DOFF# = 0 ? The model I have supports only DOFF#=1 with a fixed read

                    latency of 1.5 cycles.

                 

                Thanks,

                  Gil

                • 5. Re: Minimal Sram frequency
                  PradiptaB_11

                  Hi Gil,

                   

                  We do not have a behavioral model for DOFF# =0. We have a document that that describes the timing parameters. I am providing the link below.

                  DLL Considerations in QDRII/DDRII SRAMs

                   

                  Thanks,

                  Pradipta.