3 Replies Latest reply on Apr 27, 2020 10:15 PM by BragadeeshV_41

    SPI with 32-bit data word


      I have a feature request! The SCB SPI block only supports data sizes from 4 to 16 bits. Could Cypress grow this to 32 bits?


      How to support 32-bit transfers has been asked before a few times:

      32 bit SPI

      SPI Master 3~16 bit width limit!

      SPI TX Fifo Issues

      so this seems common enough to warrant a feature request instead of a one-off fix. So far the answer has been to "send two transfers, but also manually control slave select so that the slave doesn't see the end of the transfer", or maybe write your own in UDB. It would be nice to have it work out of the box, and without requiring CPU control of the SS line (to indicate end of data block) where it may compete with other interrupts.