3 Replies Latest reply on Apr 5, 2020 3:07 AM by KaKi_1384211

    Consulting with S25FL512S

    RoPe_2386886

      各位好

                其它几家芯片一般通过非易失寄存器、易失寄存器,或者是扩展地址,这三种方式进入或者退出4 byte addr、以及配置quad enable/dis。

      我司应用模型大部分通过非易失寄存器/易失寄存器,配置芯片的4 byte addr的进入和退出,以及quad enable/disable等。

               我司研发工程师在使用cypress的flash过程中,发现256/512Mb flash的进入和退出4 byte addr模式的命令其它三家的型号有差异,请帮忙确认是否可以做到统一,谢谢。

       

       

       

       

      MT25QL512ABB8E12-0SIT/512Mb SPI

      MX25L51245GXDI-08G

      W25Q512JVBIQ

      S25FL512SAGBHIC10
      S25FL256SAGMFIG01

       

       

       

      下面是1.8V

       

      MX25U25645GXDI00/256Mb SPI FLASH

      MT25QU256ABA8E12-1SIT/256Mb/FLASH

      S25FS256SAGBHI200/256Mb/SPI

      W25Q256JWBIQ

        • 1. Re: Consulting with S25FL512S
          ApurvaS_36

          Hi,

           

          I will clarify the process of enabling/disabling four byte address mode and quad mode for the Cypress Flash Devices mentioned.

           

          S25FL512S/S25FL256S

          There are three ways in which extended addressing can be enabled for these parts -

          The Bank Address Register configuration is as follows -

          • By default, the EXTADD bit of Bank Address Register (BAR) is set to zero. In this case, all legacy SPI commands expect only 3 bytes of address and the higher order address bits are supplied from the BAR (The default values for these higher order address bits A25 and A24 are also zero as shown in the table above). These A25 and A24 bits can be programmed to some other value (one) using the BRWR (17h) command.
          • The second configuration is when the EXTADD bit is programmed to one. In this configuration, the A25 and A24 bits are not supplied from the BAR, and all legacy SPI commands expect 4 bytes of address after the command byte.
          • The third method of addressing is by using the new commands.

           

          Let us take READ command as an example to understand this.

          • 03h command expects 3 bytes of address when EXTADD bit of BAR is set to zero. The higher order address bits are being supplied by the BAR.
          • 03h command expects 4 bytes of address when EXTADD bit of BAR is set to one. Complete 4 bytes of address need to be provided after the command byte.
          • 13h command can be used directly followed by 4 bytes of address without making any changes to the BAR.

           

          S25FS256S

          There are two ways in which extended addressing mode can be enabled for this part -

          We can understand this using explanation for READ command.

          • 03h command expects 3 bytes of address when the CR2V[7] of Configuration Register 2 is set to zero.
          • 03h command expects 4 bytes of address when the CR2V[7] of Configuration Register 2 is set to one.
          • 13h command can be used followed by 4 bytes of address without making any changes to the Configuration Register.

           

           

          All the above mentioned devices (S25FL512S/S25FL256S/S25FS256S) follow the same method for enabling/disabling the Quad mode. The QUAD bit (Non Volatile bit) in the Configuration Register 1 needs to be set or reset to enable or disable Quad mode respectively. Please note that the Single SPI commands still continue to work even when Quad mode enabled.

           

          Hope this answers your query. If not, please feel free to reach out.

           

          Regards,

          Apurva

          • 2. Re: Consulting with S25FL512S
            RoPe_2386886

            Hi ,

             

            This explains the usage of S25FLS 4byte. Do you understand that the commands to enter and exit 4 byte addr mode of 256 / 512Mb flash of MICRON(MT25QL512ABB8E12-0SIT) are the same as Cypress(S25FL512S)?

            • 3. Re: Consulting with S25FL512S
              KaKi_1384211

              Hi,

               

              Cypress S25FL512S does not have the following commands to enter 4-BYTE ADDRESS MODE Operations of Micron.
              =======
              4-BYTE ADDRESS MODE Operations
              ・ENTER 4-BYTE ADDRESS MODE: B7h
              ・EXIT 4-BYTE ADDRESS MODE: E9h
              =======

               

              Cypress S25FL51S accepts 32bit addresses by inputting the following 4Byte Address command.

              No prior register setting is required.

              Also, there is no need for 4-BYTE ENTER / EXIT commands like Micron.

              Thanks and regards,