Hi, this discussion is a follow-up on my older thread Developping CapSense trackpads with PSOC4 and 6 . I basically need a Cypress expert to validate my work before I buy the chips and fab the boards!
I have a first design of a CSX touchpad PCB with an embedded PSOC 4100S chip (CY8C4125AZI-S433).
I have mainly been referring to https://www.cypress.com/file/46081/download this design guide during my PCB design, and mainly tables 7-6 to 7-8 and figures 7-24 and 7-25 (p. 123) displayed here:
top layer (fig 7-24) bottom layer (fig 7-25)
I will now briefly describe what I managed to design so far before asking my questions!
I integrated a 7x7 CSX touchpad into my design. There are multiple resources for implementing buttons or sliders, but I find it harder to develop touchpads (I often have been referred to the 40xx pioneer kit touchpad design), this is why I wanted to share my design before prototyping to make sure there are no big design flaws. Here, we see my design. Top layer has the CSX widget, surrounded by a 25% hatched GND plane. There is another ground plane (completely filled) on the higher half of the PCB. The bottom layer has the PSoC, the traces to the capsense, and a ground plane surrounding the top layer's hatched GND plane. Basically, I tried copying the groundplanes illustrated on fig 7-24 and 7-25.
*Note that I did not implement a shield in my app, so I did not add a 17% hatched pattern to my bottom layer under my capsense widgets. The bott layer (right) is empty, there is just a ground layer surrounding the borders with vias to help reduce gnd inductance.
Top Layer Bottom Layer
1. Star connected ground. I want to make sure my ground makes sense. Here I show my ground connections viewed from my bottom layer. Does it make sense?
Next is still linked to my ground, but refers to how I designed my top layer.
2. the full ground plane on the higher half of the board is right next to my hatched ground plane, but there is a gap between them. They are not directly connected, as I believed would respect the central star ground configuration. they are connected together with vias and traces on the bottom layer as shown on the right side. I am not too sure it is what is best. Should I completely short the 2 top layer planes together and remove the gap?
Still on top layer...
3. The full ground plane on the higher half of the board goes above the capsense RX and TX traces, which I believed was a problem but fig 7-24 does exactly that. I am confused because I though this would couple GND to my traces, thus reducing Cm.
5. Right now, I have kept the solder mask above my sensing elements, but in my last design, I removed it completely, so my sensing elements were bare copper. Which one is best? If I keep the solder mask, can I write silkscreen directly on top of my elements? I wanted to write like RX1, TX2, etc. on the corresponding elements
6. As one last small question, I was wondering if adding mounting holes and screws on the corner of my board could be a problem with capsense? I think I have read this somewhere in the documentation but I can't find it anymore.
There are quite a few questions in my thread, I am sorry, but I tried to be as clear as possible so the most people could benefit from your answers! Thanks again.