Parameters in the Verilog code above are "static", they are being passed from the Dialog menu to the Verilog code on startup and that's it. They can't be changed during the run-time. Of course, they can be read back in firmware, but it is not possible to change them; e.g. in ShiftMUX.h file:
#define `$INSTANCE_NAME`_REG0 `=$REG0` // now REG0 is available to code
Generally, to have tunable parameter inside the Verilog code, a Control or Status Register should be instantiated inside the code and then it can be accessed using API like a standard Register. Please see basic example here
The issue in your case is that it needs 9 x 16-bit registers (each one constructed of 2x 8-bit register), total 18 registers. I am afraid that it will be hard to fit PSoC PLD space. Also note that writing to combined 16-bit register is not atomic, which can be an issue.
To test the design I would recommend to build a project using schematic first, where Registers are sitting outside the "Core" component ( written in Verilog) and connected by buses. If successful, design can be compacted into the Verilog.