3 Replies Latest reply on Mar 30, 2020 10:48 PM by JayakrishnaT_76

    Question about CYUSB306X power-up sequence requirements

    JaDu_4088601

      Q1) We have tied MIPI_RESET to GND through a pull-down resistor and don’t have a way to drive this pin high (by design). We only control the input to the RESET# pin. So presumably we can ignore the requirement for MIPI_RESET# that is depicted in the timing diagram of the datasheet (Figure 4 on page 10 of document number 001-87516 Rev. *N)?

       

      Q2) The attached PowerPoint slides depict the voltages in the timing diagram at power-up and power-down. I believe we comply with all the requirements in the timing diagram, but I am concerned about the fact that VUSB is not a monotonically rising signal. Although VUSB starts to rise before all other voltages and quickly reaches 4V, it then drops down to around 2.5V. Eventually VUSB rises again to its steady state value of ~5V but this doesn’t happen until after the other voltages have reached steady state. Is this a cause for concern?

       

      Thanks,

      James

        • 1. Re: Question about CYUSB306X power-up sequence requirements
          JayakrishnaT_76

          Hello,

           

          Please find my comments for your questions below:

          1. The MIPI_RESET should be pulled down to ground using 10K resistor (as mentioned in the datasheet).

          The CX3 chip will internally drive this pin high during power up. You don't need to connect any external component for the same.

           

          2. From the datasheet, VUSB should be within 4-6V. As VUSB drops down to 2.5V and stabilizes only after all other power domains stabilize, this can be a cause for concern. Please let me know if the device is enumerating properly. Also, share the schematic so that I can evaluate it on my end.

           

          Best Regards,

          Jayakrishna

          • 2. Re: Question about CYUSB306X power-up sequence requirements
            JaDu_4088601

            Hi Jayakrishna,

             

            Thanks for your reply.

             

            Regarding question #2, VUSB is the input voltage to a PMIC that generates the other voltages for the CX3 (AVDD, VDD, VDD_MIPI, VDDIOx, and CVDDQ). As such, I can change the UV/LO input threshold on the PMIC such that the other voltages don't start to enable until after VUSB reaches ~3.5V. After this, VUSB continues to rise monotonically until is stabilizes, and so it won't dip below 4V whilst the other votlages are coming up. Unless you foresee any issues, I think I will take this approach.

             

            In response to your question, we have not seen problems with enumerating on a consistent basis. However, we have some units that behave sporadically, so I think this issue might be a factor. I'm not able to send the schematic at this time because technically it belongs to our customer (we are the ODM/OEM) but should it become necessary to distribute I can seek their permission.

             

            Regards,
            James

            • 3. Re: Question about CYUSB306X power-up sequence requirements
              JayakrishnaT_76

              Hello,

               

              Can you please share the current waveform on VUSB.

              Also, the workaround you mentioned in your previous response should be fine taking into consideration that the Power up sequence mentioned in fig 4 of the CX3 datasheet is not violated.

               

              Best Regards,

              Jayakrishna