4 Replies Latest reply on Mar 30, 2020 12:05 AM by ReBa_1054056

    Which protocol over I2C is used for CapSense tuning

    ReBa_1054056

      I'm using the CY8CKIT-145-40XX which I can program and tune via the KitProg2 and the 'PSoC Creator Tuner'. Via USB-I2C this program accesses the parameters within the PSoC4. Slider parameters like the RawCounts, Baseline, DiffCounts, Status and Position (shown in the Graph View) can be read.

      Which protocol is used over I2C to the EZI2C of the PSoC4 to read these parameters?

      Has this been documented?

      Is an API available (preferably in C) by which an external device (like EZ-USB FX3S) can access these low level CapSense tune parameters via I2C? So the external processor being the I2C master and the PSoC4 the EZI2C slave.

       

      Rene

        • 1. Re: Which protocol over I2C is used for CapSense tuning
          BragadeeshV_41

          Hi ReBa_1054056,

           

          The CapSense parameters such as hardware parameters, software parameters and other raw data such as RawCounts, Baseline, DiffCounts etc are available inside the data structure name CapSense_dsRam. If you wish to access these parameters, we recommend use the CapSense_GetParam and CapSense_SetParam APIs. Refer to the following article:

          Access and Modify CapSense Register Map in Firmware – KBA2226674

           

          Regards,

          Bragadeesh

          • 2. Re: Which protocol over I2C is used for CapSense tuning
            ReBa_1054056

            The function CapSense_GetParam()and CapSense_SetParam()are CapSense low level API function and part of my PSoC Creator project. So not usable from within the FX3S. The FX3S is the external processor connected to the EZI2C port.

            This Export Register Map (the article mentions) provided me with the RAM register map of my CapSense design.

             

            Is it possible to access these registers through the EZI2C port? So the FX3S I2C master can read for example the CONFIG_ID at address 0x00 or SLD_SNS_CP0 at 0x108?

            The EZI2C configuration has Number of addresses: 1, Primary slave address (7 bits): 0x08, and Sub-address size (bits): 16. The PSoc 4 Serial Communication Block (SCB).pdf (the datasheet of the EZI2C component) gives a description of the Interface as Seen by an External Master.

            Is the Sub-address mentioned here the same address as the one in the RAM register map?

             

            Rene

             

            • 3. Re: Which protocol over I2C is used for CapSense tuning
              BragadeeshV_41

              Hi ReBa_1054056,

               

              Is it possible to access these registers through the EZI2C port? So the FX3S I2C master can read for example the CONFIG_ID at address 0x00 or SLD_SNS_CP0 at 0x108?

               

              -> Yes, you can access these registers through the EZI2C port once the CapSense_dsRam is set as the EZI2C buffer.

               

              Is the Sub-address mentioned here the same address as the one in the RAM register map?

               

              -> Yes, they both are the same. Please set sub - address size to 16 bits for CapSense datastructure

               

              Use the following addresses (sub - address) to access the data bytes from the master.

               

              You can use one of the following commands to read the registers:

              Start | Slave_Address + Write | Sub_Address (2_bytes) | Stop

              Start | Slave_Address + Read |  No_of_Bytes_to_Read | Stop

               

              (Or)

               

              Start | Slave_Address + Write | Sub_Address (2_bytes) | Repeated_Start | Slave_Address + Read |  No_of_Bytes_to_Read | Stop

               

               

              Regards,

              Bragadeesh

              • 4. Re: Which protocol over I2C is used for CapSense tuning
                ReBa_1054056

                Thank you. It's all clear now.

                 

                Rene