CPLD board work with 3014 failed

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jori_4613131
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HI, there,

Good day.

I am developing on Superspeed Explorer Kit(CYUSB3014 inside), and CYUSB3A-007(Xilinx CPLD inside). I want to use CPLD as MasterFifo while the FX3 as slavefifo.

But there are problems when using  the examples(superspeed design example v1.2.1 download from Cypress) .

  1. I found there is no clock input for CPLD board, so I guess the FX3 must use its internal clock, but “SlaveFIFO_Example“ of the firmware project can not output this clock, how would it work without clock?
  2. Open the CPLD project of CPLDASMASTER , there are several questiosn I do not understand. for one thing is the pins's locations are not correct when compare with explorer kit, such like the PushButton do not have real button, the "RD" and "WR" pins of USB3014 are not  correspond to real ones, and they are only three flags in the firmware while four in CPLD project, for the other thing is there is no "CS" and "OE” pins for USB3014 in CPLD project, will it work then?

For all of problems above, I guess I must miss some important steps when using these two boards and this example.

Please give some suggestions. What I earge to know is whether you have mature example that the users can develop directly on the two boards.

thanks

Jiayou

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1 Solution

Hello,

For transferring data from PC to CPLD, you can make use of the following procedure:

1. Load CPLDasFifoMaster.xsvf code into the CPLD.

2. Set CPLD Switches 6, 7 and 8 to Open (Pressed side of the switch is next to the printed word open). This is done to select Write Mode.

3. Now load GPIF_Example5.img into FX3 using control center application.

4. The example will enumerate as USB Streamer Device.

5. Press SW2 of the explorer kit.

6. Select the OUT Endpoint and perform the data transfer. You can transfer a file by hitting transfer file-OUT button corresponding to OUT endpoint in the control center.

For performing bidirectional data transfers, you can make use of the same code for the CPLD but the switches 6,7 and 8 need to be changed while you perform a read operation. The switches should be closed to perform read operation and open for performing write operation. But you need to program FX3 with the example GPIF_Example6 for performing bi-directional transfers.

Best Regards,

Jayakrishna

Best Regards,
Jayakrishna

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JayakrishnaT_76
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First question asked 1000 replies posted 750 replies posted

Hello,

Please let me know which example project (from superspeed design example v1.2.1) are you trying to test so that I can understand the problem and help you better.

Best Regards,

Jayakrishna 

Best Regards,
Jayakrishna
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HI, Jayakrishna ,

thanks for your quick reply.

I am using,

CPLDasFifoMaster in CPLD Project folder and

SlaveFIFO_Example in FX3 Firmware Project.

at the beginning I am not even revise the code, but after checking CPLD project with Firmware project, I found they are not march.

DO I have to revise codes(where and how) to make the two boards(CYUSB3KIT-003 and CYUSB3ACC-007) work properly, and I prefer the CPLD to act as MasterFifo.

thanks

Jiayou

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HI, Jayakrishna ,

thanks for your quick reply.

I am using,

CPLDasFifoMaster in CPLD Project folder and

SlaveFIFO_Example in FX3 Firmware Project.

at the beginning I am not even revise the code, but after checking CPLD project with Firmware project, I found they are not march.

DO I have to revise codes(where and how) to make the two boards(CYUSB3KIT-003 and CYUSB3ACC-007)  work properly, and I prefer the CPLD to act as MasterFifo.

thanks

Jiayou

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Hello,

The superspeed design example v1.2.1 has some projects that can be used to make FX3 as a source or sink of data and for bidirectional data transfers. Please let me know in which configuration do you want to use FX3. Is it like you want to write some data from CPLD to FX3 or is it that you want to write data from FX3 to CPLD.

Also, to understand about the CYUSB3ACC-007, we recommend to read the book "SuperSpeed Device Design by Example" by John Hyde. The book is available on Amazon as well as Kindle. Please refer to the below page.

http://www.cypress.com/documentation/other-resources/superspeed-device-design-example-john-hyde

Best Regards,

Jayakrisha

Best Regards,
Jayakrishna
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HI,

actually I want its bulk out funciton, where PC send bulk of data to FX3, and FX3 transfer all to CPLD/FPGA,

it wll be perfect it could perform Bulk In function as well.

thanks

Jiayou

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Hello,

For transferring data from PC to CPLD, you can make use of the following procedure:

1. Load CPLDasFifoMaster.xsvf code into the CPLD.

2. Set CPLD Switches 6, 7 and 8 to Open (Pressed side of the switch is next to the printed word open). This is done to select Write Mode.

3. Now load GPIF_Example5.img into FX3 using control center application.

4. The example will enumerate as USB Streamer Device.

5. Press SW2 of the explorer kit.

6. Select the OUT Endpoint and perform the data transfer. You can transfer a file by hitting transfer file-OUT button corresponding to OUT endpoint in the control center.

For performing bidirectional data transfers, you can make use of the same code for the CPLD but the switches 6,7 and 8 need to be changed while you perform a read operation. The switches should be closed to perform read operation and open for performing write operation. But you need to program FX3 with the example GPIF_Example6 for performing bi-directional transfers.

Best Regards,

Jayakrishna

Best Regards,
Jayakrishna
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thanks and that helps.

One more question, do you know the GPIF II project for these GPIF_Example5 and GPIF_Example6  locate?

Since the CPLDasMaster project postion is easy to find, and guess it is original and donot need any revise, right?

thanks

JIayou

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Hello,

The GPIF II projects for these projects can be found in the following location:

..\Superspeed Design Examples\SuperSpeed Design Examples V1.2\GPIF II Projects

The FX3 Projects for the same can be found in

..\Superspeed Design Examples\SuperSpeed Design Examples V1.2\FX3 Firmware Projects

Please note that I haven't added the full path as it will be different for you depending on where you installed the files.

You need not do any revision to any of the projects as it would work without any revisions.

Best Regards,

Jayakrishna

Best Regards,
Jayakrishna
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Hi, Jayakrishna,

I checked the SlaveFIFO_Example in GPIF project(while CPLD as MasterFIFO), but there is no pin connection for SW2.

pastedImage_3.png

Here are the hardware connection screenshot.

pastedImage_7.png

So I guess the GPIF project is not the one correct for this one, but not even one after check all GPIF projects.

any advices?

thanks

Jiayou

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here is CPLD connection missing.

pastedImage_0.png

the "PushButton" in the pic connect to CTRL[9], not GPIO45.

I hope I said it clearly.

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Hello,

Your finding is correct. But, even though CTL[9] is not used in the GPIF II designer, its value is configured through firmware. Please refer to the source file RunApplication.c in the example project GPIF_Example5. The snippet is attached below:

pastedImage_0.png

The function DebounceTimerExpired will be triggered every 20ms. When this is triggered, the state or value of GPIO 45 (defined by the macro PUSH_BUTTON) is copied to the value. Then, the state of GPIO 26 (defined by the macro CPLD_PUSH_BUTTON) will be updated by the same value. By this way, when you press the SW2 (GPIO 45), the state of CTL9 (GPIO 26) will be updated. Hence, CPLD will get this input.

Best Regards,

Jayakrishna 

Best Regards,
Jayakrishna

Thanks for your answer.

Another thing found we donot even set all CPLD Switches 6, 7 and 8 to be open, only 7 is enough from the code of CPLD for reading.

pastedImage_0.png

And I test this case, it works fine after several Bulk Out tries.

regards

Jiayou

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Hi,

I was wondering that why GPIF project(for both GPIF_Example5 and GPIF_Example6) set to be Master, since the CPLD act as Master already.

pastedImage_0.png

Do we need to reset it to Slave interface? or just leave it go?

please advices.

Thanks

Jiayou

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Hello,

You need not change the Interface type from Master to Slave in GPIF II designer. The example is tested with the interface type being Master. So please do not change it to slave.

Best Regards,

Jayakrishna

Best Regards,
Jayakrishna
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OK.

I will try to use all the codes from this example, and immigrate to new FPGA, since the AN65794 have problems when using relative large file transmission(~2MB).

thanks so much for your help.

Good day

Jiayou

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Hello,

Thanks for the update.

Good Day!

Best Regards,

Jayakrishna

Best Regards,
Jayakrishna
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