3 Replies Latest reply on Mar 25, 2020 10:47 PM by AH_96

    Developping CapSense trackpads with PSOC4 and 6

    JeSi_4326976

      Hi, I am working with PSOC 6 on a CSX trackpad project. My first iteration used an external 5x5 trackpad PCB connected to the PSOC 6 BLE pioneer kit like so:

      90526621_553068038925306_3483652217213288448_n.jpg

      This pad works great, has a SNR ratio of 6.5, total scan time 8ms with a square electrode side lenght of 9 mm as shown here:

       

      figure_2_garrett_blog.png

       

      Here are my questions for further development with capsense:

       

      1. In a previous project, we used CSD and we were able to set the bit resolution of the scans (CSD can set their resolution from 6 to 16 bits, reducing the resolution helped us reduce the total scan time. I know CSX components are not supported by smartsense, so I should be able to set my trackpad widget's resolution but this feature does not seem to exist for this widget in Widget hardware parameters in the advanced tab. Is there a way to tweak reading speed with my CSX trackpad?

       

      2. I have looked into the PSoC® 4 and PSoC 6 MCU CapSense® Design Guide document but did not find an answer to this question yet: Can I further reduce the electrode size? and if so, up to what point? my project involves creating a tactile sensing mechanism for robots, so I would try reducing electrode size to a minimum (Maybe 5mm side size?) Is this feasible with a capsense CSX trackpad widget? (It probably will reduce the SNR, and it is already at 6.5..) where can I find the minimum pad size documentation?

       

      3. I was planning on buying the 4100S series devboard https://www.cypress.com/documentation/development-kitsboards/cy8ckit-041-41xx-psoc-4100s-capsense-pioneer-kit

      Since I want my next iteration to contain the PSOC on the PCB, I wanted to go for PSoC 4 for prototyping with capsense, as psoc 6 only has BGA packages and would require 4 layer PCBs and additional development time and $.

      My question #3 is: since 4100S contains the capsense 4th generation, I shouldn't encounter any problem transfering my application settings from PSoC6 to 4100S right?

       

      Thank you for your continuous support!

        • 1. Re: Developping CapSense trackpads with PSOC4 and 6
          AH_96

          Hi JeSi_4326976

           

          1. The scan time in CSX is dependent on the number of sub-conversions and the Tx clock speed. Scan time = (N / (Tx Clock freq)), where N = number of sub-conversions.

          Increasing number of sub-conversion results in increased signal but also increases the scan time.

           

          2. If you observe the CY8CKIT-041-40xx design files, the touch pad size is 3.5 mm each side. This can be implemented in your design as well and will provide a reliable response.

           

          3. If your project was built in PSoC Creator then the porting is straightforward, the same code can be used. And, it is recommended to use PSoC 4S part over the PSoC 6 for CapSense since there is a noise issue in PSoC 6. CapSense sensors should be assigned to port 6 and 7 only in PSoC 6 (refer the errata section in PSoC 6 datasheet).

           

          Thanks,

          Hari

          2 of 2 people found this helpful
          • 2. Re: Developping CapSense trackpads with PSOC4 and 6
            JeSi_4326976

            This was a very complete answer, thank you so much! I bought the 4100S kit this morning!

             

            It brings other questions to mind:

             

            1. After refering to the CY8CKIT-041-40xx design files you shared, I think my first design was flawed. the CY8CKIT pad has half electrodes at its border. This means, if I understand correctly, that the RX-TX pairing of a single sensing element should be best in the middle of the X formed by the electrodes, as illustrated here:

            Untitled.png

             

            And that would mean the full electrodes bordering my design were useless and slicing them in half would have helped increasing sensing area?

             

            figure_2_garrett_blog.png

             

            2. So the CY8CKIT-041-40xx 's trackpad electrode side length is 3.5mm. That's great! is there a reference in the datasheet that would help me understand what are the limitations, minimum side length, and its influence on other parameters of the capsense application (for instance, a formula that would determine how SNR is influenced by electrode size)

             

            3. I never programmed PSOCs on PCBs before, but I plan to do for my next iteration. I was thinking of using a miniprog kit like this one https://www.cypress.com/documentation/development-kitsboards/cy8ckit-002-psoc-miniprog3-program-and-debug-kit and add a JTAG connector to my PCB. Is this the optimal way (when using capsense, in case some pins have conflicting functionalities)?

             

            4. When looking at different 4100S and 4100S Plus chips available on digikey,  https://www.digikey.ca/products/en/integrated-circuits-ics/embedded-microcontrollers/685?k=psoc%204100s Are all the options just different packages (except for differences between 4100S and 4100S plus)? If not, is there a document that explains what CY8C4147AZI-S455 has vs CY8C4125LQI-S423 for example?

             

            Thank you again

            • 3. Re: Developping CapSense trackpads with PSOC4 and 6
              AH_96

              Hi JeSi_4326976

               

              1. The way CSX touch-pad works is that it excites one row of electrodes called the Tx electrode. It provides a square wave along one row and senses each column for any activity (called Rx electrode). So it is the area between the Tx and Rx that contributes to signal. In the current design, you can add half electrodes in the top layer to increase the sensing are (as you have mentioned).

              Whenever there is a finger, the mutual capacitance between the Tx and Rx electrode will reduce and this is sensed by the CapSense IP.

               

              2. We are working on updating the design guide with these information. At present, the reference touchpad layout is the recommended design.

               

              3. Yes. Miniprog3 is the preferred programming tool. You can have a 5 pin connector with SWDIO and SWDCLK lines to the correcponding pins in the IC to program/debug. If the SWD pins are used for CapSense design, the device can still be programmed, but debug functionality will not be present.

               

              4. No, PSoC 4100S and 4100S plus are different architectures and are different family of controllers. PSoC 4100S Plus has a newer CapSense IP compared to 4100S. The PSoC 4100S Plus family of devices offer larger flash memory, more peripherals, and more I/Os when compared to the PSoC 4100S. You can refer this KBA for referenece: Differences between PSoC 4100S Plus and PSoC 4100S Family of Devices - KBA222580

               

              Thanks,

              Hari