How to change the ADC scan rate

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ViSh_3577471
Level 2
Level 2
10 replies posted 5 replies posted 10 questions asked

Hi

My kit is PSoC63.I can find some  information from ADC datasheet .The achieved scan rate is dependent on the following:

▪ ADC clock rate

▪ Number of channels

▪ Averaging

▪ Resolution

▪ Achieved acquisition time

The parameters of number of channels ,averaging and resolution are fixed,  so which API  can change the scan rate ?

Best regards, vick.

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1 Solution

你可以直接看datasheet page 5,6,7, 之前我的回复里面把问题描述复杂了。

SAR ADC的时序图如下:

pastedImage_6.png

采样速率的计算公式为:

pastedImage_7.png

总共是18个clock周期。

如果你想达到改采样速率的目的,那么你可以改ADC的时钟。

如果你想获得achieved scan rate = 1MSPS,

环境的基本设置参数:channel =1, no average, resolution =12, achieved acquisition time =167ns,

倒推过去,你需要设置ADC的clock设置成18Mhz,其它的速率也是同样的方式。

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3 Replies
LinglingG_46
Moderator
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500 solutions authored 1000 replies posted 10 questions asked

scan rate 不能直接通过API设置。 scan rate 是由 (▪ ADC clock rate▪ Number of channels▪ Averaging▪ Resolution▪ Achieved acquisition time)这几个因素决定的,具体的计算方法查看datasheet的page 5,6,7。

那么如果想修改scan rate,在channel数,分辨率,平均数都是fix的情况下,我们可以修改ADC clock,具体的修改方法如下:

For example:

PeriCLK是50Mhz,ADC的clock是从PeriCLK分出的,想得到一个1us的sample time的例子。

1us = 1/(50/3/17)

那么ADC的时钟可以设置成50MHZ的三分频,50/3 = 16.67MHz,这一步的设置方法是:

/* Configure the clock for the SAR for a 16.67 MHz clock frequency. */

Cy_SysClk_PeriphAssignDivider(PCLK_PASS_CLOCK_SAR, CY_SYSCLK_DIV_8_BIT, 1u);

Cy_SysClk_PeriphSetDivider(CY_SYSCLK_DIV_8_BIT, 1u, SAR_TARGET_CLK_DIVIDER - 1u);

Cy_SysClk_PeriphEnableDivider(CY_SYSCLK_DIV_8_BIT, 1u);

接着需要得到1us,就是16.67 MHz的17的cycle,也就是需要设置成Sample Time为18,这个值到实际计算的时候是要减去1的,所以需要多设置1。

* Set the sample time to meet the DieTemp settling time requirement of 1 us.

* With a 16.67 MHz SAR clock, 17 cycles (or a value of 18 in the register)

* gives an aperture time of 1.02 us. */

#define CONFIG1_SAMPLE_TIME01       ((18 << CY_SAR_SAMPLE_TIME0_SHIFT) \

                                    | (4 << CY_SAR_SAMPLE_TIME1_SHIFT))

同样,如果想得到50 ksps 的scan rate,那么可以做如下设置:

/* Set the aperture times to target a 50 ksps scan rate.

* Recall that the SAR clock is 16.67 MHz.

* Sample Time 0 is set to 302 clock cycles.

* Sample Time 1 is set to 4 clock cycles. */

#define CONFIG0_SAMPLE_TIME01       ((302 << CY_SAR_SAMPLE_TIME0_SHIFT) \

                                    | (4 << CY_SAR_SAMPLE_TIME1_SHIFT))

总结一下:

为了得到一个scan rate,有两个地方需要配合配置,第一ADC的输出时钟,第二就是SAR_SAMPLE_TIME01 需要配置cycle。根据提供的参数, 具体的计算方法参考datasheet的第5,6,7页。 可以参考creator中的示例工程CE220974。

希望我的回复能对你有所帮助。

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您好,非常感谢您的回复。有两个问题想向您咨询

第一个:您提到接着需要得到1us,就是16.67 MHz的17的cycle,也就是需要设置成Sample Time为18,

根据公式计算:

ch0 acq.time=17/16.67M=1.02us,ch0 sample time =1.02us+(12位+3)/16.67M=1.92us 不等于您说的sampletime=1us

另外如果计算ch1 acq.time=180ns,ch1 sample time=1.08us

total sample time =1.92+1.08=3us 所以不太明白您指的sample time为1us是什么意思?

第二个问题:请问  SAMPLE_TIME01是指什么?sample time 0是代表ch0通道采样间隔时钟数吗?另外,18 左移CY_SAR_SAMPLE_TIME0_SHIFT是什么意思?

#define CONFIG1_SAMPLE_TIME01       ((18 << CY_SAR_SAMPLE_TIME0_SHIFT) \

                                    | (4 << CY_SAR_SAMPLE_TIME1_SHIFT))

PDL中相关表述为:

uint32_t sampleTime01
Sample time in ADC clocks for Sample Time 0 and 1.

谢谢您!

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你可以直接看datasheet page 5,6,7, 之前我的回复里面把问题描述复杂了。

SAR ADC的时序图如下:

pastedImage_6.png

采样速率的计算公式为:

pastedImage_7.png

总共是18个clock周期。

如果你想达到改采样速率的目的,那么你可以改ADC的时钟。

如果你想获得achieved scan rate = 1MSPS,

环境的基本设置参数:channel =1, no average, resolution =12, achieved acquisition time =167ns,

倒推过去,你需要设置ADC的clock设置成18Mhz,其它的速率也是同样的方式。

0 Likes