Internal UART Connections/Loopbacks, why can't I? Or, can I?

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TeKu_4507141
Level 1
Level 1
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I want to do this, but I get errors as soon as I make the connections.  Is there a way to do this without going to external pins on the device?

The reasons for needing to do this are complicated, and stupid.  Nevertheless, it's what someone is asking for, and I'm trying to accommodate.

pastedImage_0.png

Errors:

pastedImage_1.png

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MotooTanaka
Level 9
Level 9
Distributor - Marubun (Japan)
First comment on blog Beta tester First comment on KBA

Hi,

This was an interesting challenge!

At first I tried with single UART.

Directly connected tx_out and rx_in.

And could not generate application. (NG)

001-Loopback_direct.JPG

Then I tried it with SmartIO

Generate Application succeeded! (OK)

NOTE: This is the only case I had a success this morning. orz

000-loopback_SmartIO.JPG

Then as using SmartIO seemed to be promising,

I tried with two UARTs, using SmartIO's data ports only.

And Failed (NG)

002-two_uart_SmartIO.JPG

Then I tried to use GPIO ports of SmartIO

And failed (NG)

003-two_uart_SmartIO_via_GPIO.JPG

Then I decided to go with UDB (and Verilog)

Failed. (NG)

004-verilog_inter_connect.JPG

Just in case, I added REG (and clock) in the Verilog component.

.. alas ... (NG)

005-verilog_inter_connect_dff.JPG

So currently my conclusion is

(1) I can loop back a UART using SmartIO

(2) I can not loop back a couple of UARTs connected together.

moto

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MotooTanaka
Level 9
Level 9
Distributor - Marubun (Japan)
First comment on blog Beta tester First comment on KBA

Hi,

This was an interesting challenge!

At first I tried with single UART.

Directly connected tx_out and rx_in.

And could not generate application. (NG)

001-Loopback_direct.JPG

Then I tried it with SmartIO

Generate Application succeeded! (OK)

NOTE: This is the only case I had a success this morning. orz

000-loopback_SmartIO.JPG

Then as using SmartIO seemed to be promising,

I tried with two UARTs, using SmartIO's data ports only.

And Failed (NG)

002-two_uart_SmartIO.JPG

Then I tried to use GPIO ports of SmartIO

And failed (NG)

003-two_uart_SmartIO_via_GPIO.JPG

Then I decided to go with UDB (and Verilog)

Failed. (NG)

004-verilog_inter_connect.JPG

Just in case, I added REG (and clock) in the Verilog component.

.. alas ... (NG)

005-verilog_inter_connect_dff.JPG

So currently my conclusion is

(1) I can loop back a UART using SmartIO

(2) I can not loop back a couple of UARTs connected together.

moto

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Wow, thanks Motoo for trying all those different solutions!