This was an interesting challenge!
At first I tried with single UART.
Directly connected tx_out and rx_in.
And could not generate application. (NG)
Then I tried it with SmartIO
Generate Application succeeded! (OK)
NOTE: This is the only case I had a success this morning. orz
Then as using SmartIO seemed to be promising,
I tried with two UARTs, using SmartIO's data ports only.
And Failed (NG)
Then I tried to use GPIO ports of SmartIO
And failed (NG)
Then I decided to go with UDB (and Verilog)
Just in case, I added REG (and clock) in the Verilog component.
.. alas ... (NG)
So currently my conclusion is
(1) I can loop back a UART using SmartIO
(2) I can not loop back a couple of UARTs connected together.
Wow, thanks Motoo for trying all those different solutions!