1 Reply Latest reply on Mar 19, 2020 5:39 AM by LePo_1062026

    Gated timer mode


      Hello everyone.

      I'm just starting with PSoC devices, and was reading the datasheet for the timer component in PSoC Creator. Component Debug Window section states about timer registers which are described in the device trm. So I read the Timer, Counter, PWM section of the PSoC5LP TRM, and found that the fixed function timer has many modes available, such as: pulse width, period or stop on interrupt modes in gated timer mode and a few more. For example period mode means that the timer starts and stops on the rising edge on the enable input. But I can't see this mode in the timer component inside PSoC creator. The trm states that to enable period mode, two bits of TMRx_CFG2[1:0] should be set to 10. But PSoC5LP Registers TRM states that these two bits are reserved. My questions are:

      1. Does any component in PSoC Creator use this and the other mentioned modes?

      2. Are they available at all? Can I program the timer to use them?

      3. Why the timer component datasheet says that the fixed function implementation has two-cycle lag with respect to the enable input, whereas the PSoC5LP TRM states that the timer has only 1-cycle lag?



        • 1. Re: Gated timer mode



          You are correct.  There is some confusing information regarding the Timer (FF).


          To allow for the HW enable line, the Enable Mode = Software and Hardware.


          As you pointed out TMRx_CFG2[1:0] is used to control how the enable signal effects the Timer counting.  However the Register TRM indicates these bits are reserved.


          The user can directly manipulate these bits (at their own risk).  There does not appear to be any API calls to change the Timer FF enable modes.


          It's possible, that Cypress chose to limit enable signal control on this fixed function block.