Hello JaBe_1397886 ,
For (1) The GPIOs can continue to drive when the PSoC 3 device is in a low-power mode. This is helpful when you need to hold other external logic at a fixed level, but it can lead to wasted power if the pins needlessly source or sink current.
Any unused GPIO should be configured as Analog Hi-Z unless there is a specific reason to use a different drive mode.
For more information on this please refer to the PSoC 3 and PSoC 5LP low power mode and power reduction technique appnote: https://www.cypress.com/file/45776/download
For (2) UDB-based Components, such as control registers, are typically not active during sleep or hibernate. They can glitch when the PSoC device enters or exits these modes. Section 3.11 page 15 of the above mentioned appnote describes this in detail.
Can you please attach the project so that we can a look at it, this will enable us to figure out why the device is waking up at 1.2 seconds.
According to my understanding you are using CTW as the wakeup source for the device. You should use the PM_SLEEP_TIME_CTW_2048MS macro to configure the wakeup period as two seconds when calling CyPmSleep() or CyPmAltAct().
(see page 30 of the appnote)