4 Replies Latest reply on Mar 16, 2020 10:13 PM by MoTa_728816

    Chip capabilities are confusing and not consistent

    MiBa_4637081

      New to PSOC so maybe I'm missing something, but I seem to keep finding inconsistencies between the website and reference docs.

       

      My starting requirements were pretty simple: 2 UART ports, 1 SPI, CapSense.  Based on SCB documentation it seemed like that would mean 3 SCB blocks minimum.

       

      Based on the "Getting started with PSoC 4" doc (https://www.cypress.com/file/46106/download), it seems like I should be able to use any PSoC 4 family for CapSense, but am limited to 4100S, 4100S+, 4100PS, 4200L, or 4500 for the SCBs.  I bought the CY8CKIT-043 to test some things and immediately hit one contradiction, the datasheet and webpage for the chip on the devboard contradict the getting started doc on the number of SCBs.  I figured this was a one-off but while looking for a cheaper and smaller chip for my purposes I kept running into things like this.

       

      The final example that has really put me off is in regards to the CY8C4125AZI-M443 chip.  I had to find it in the PSOC Creator device selector because the Cypress web-based parametric search doesn't seem to include CapSense (another thing I felt like I must be missing but just couldn't find) and DigiKey has some incorrect info.  This chip is part of the PSoC 4100M series, which according to the getting started doc doesn't even exist.  Now looking at the number of SCBs, Creator says it has 3, the webpage (https://www.cypress.com/part/cy8c4125azi-m443 ) says it has 4, the datasheet (https://www.cypress.com/file/139961/download ) says 4, and of course the getting started doc doesn't say anything.  I created a project with this chip and in reality it seems to only have 2, as it refuses to build with 2 UARTs and an SPI (or 3 SPI that I did as a test, attached).

       

      I really hope someone can make sense of this and explain how it's all consistent and what I'm missing.  I would love to use Cypress chips, they seem to have some great features with the SCB and programmable analog stuff, but I just can't if I can't trust the documentation to be consistent, much less correct.

        • 1. Re: Chip capabilities are confusing and not consistent
          MoTa_728816

          Hi,

           

          I also felt that the device selector in the web is not as friendly as we would like.

          So I have used device selector in PSoC Creator.

          But just to make sure I tried the we by myself.

           

          At first the Parts Selector

          000-default.JPG

          If I click "Show/Hidden Parameters", the "secret" dialog appears.

          I could see "CapSense" in the "Hide" list

          001-show-hidden.JPG

          So I selected "CapSense" and dragged it to "Show" from "Hide"

          WS000004.JPG

          WS000007.JPG

          WS000008.JPG

          Then "CapSense" showed up in the list "magically"

          WS000010.JPG

           

          moto

          P.S. To be honest, I, myself would stay with the device selector of the PSoC Creator though ;-P

          • 2. Re: Chip capabilities are confusing and not consistent
            MoTa_728816

            Hi,

             

            As you wrote 2 x UART and 1 x SPI and CapSense,

            I copied and modified your project's schematic as

            003-schematic.JPG

            Then I could generate application

            002-uartx2-spix1.JPG

            But in your attached project, the schematic had 3 SPIs

            001-schematic.JPG

            As you may know, a SPI requires 3 ~ 4 pins, MISO, MOSI, SCLK, and SS0,

            if you have more salves SS1, SS2..

             

            On the other hand, UART usually requires 2 (RX, TX).

             

            When I tried to generate application of your schematic, the error was

            002-error.JPG

            This is not that the device does not have enough SCBs,

            but the internal circuit of the device could not connect all pins of 3 x SPIs.

             

            Although this is somewhat sad, in many MCUs,

            we can not fully use the internal components

            because of the limitation of their packages and/of configurations.

             

            BTW, since we can use 2 x UART and 1 x SPI and CapSense, can you survive with that device?

             

            moto

            • 3. Re: Chip capabilities are confusing and not consistent
              MiBa_4637081

              That's good to know about the web selector, thank you.  I honestly prefer the web selector just because its easier to copy paste and open the part listing.

               

              However, for me the application does not build with 2x UART and 1x SPI either.  I get a similar error.

              How were you able to get it to build with those settings?

               

              Also, are you able to offer any advice on why there is conflicting info between different sources and what is actually correct?

              • 4. Re: Chip capabilities are confusing and not consistent
                MoTa_728816

                Hi,

                 

                I only copied your project and placed a couple of UARTs and a SPI.

                 

                Attached is the project I made.

                 

                moto