1 2 Previous Next 27 Replies Latest reply on Apr 10, 2020 12:24 AM by YaZh_4656101

    FX3 sends data to FPGA with FlagA problem

    YaZh_4656101

      Dear all,

      Before I used EZ-USB FX2 to transfer data, FlagA was always 0.

      When I press "Bulk OUT"  FlagA will change from "L" to "H" and the FPGA will receive the data.

      I want to use FX3 sends data to FPGA,but FPGA never receives data.

      I use logic analyzer to check the signal.Found that FlagA is always "H".

      when I didn't send any data(Idle) or I press "Bulk OUT" that FlagA is always "H".

      So I want to know how to make FlagA become "L".

      Thanks!

       

       

       

       

        • 1. Re: FX3 sends data to FPGA with FlagA problem
          RashiV_61

          Hello,

           

          Please let me know which firmware are you using for for testing slave FIFO interface with FX3

          If you are using the default firmware with the AN75974 application note, socket 3 i.e. the address lines should be 3 (binary: 11) is the consumer and Flag C  indicates the status of the DMA buffer. Flag C is high initially (Full) and it asserts low when data is read from FX3.

          Please refer to AN65974 read sequence, to read data from FX3.

           

          If you are using custom firmware, please share the project files and also the timing sequence of signals at GPIF interface

           

          Regards,

          Rashi

          • 2. Re: FX3 sends data to FPGA with FlagA problem
            YaZh_4656101

            Hello,

            Thank you for your reply.

            I did not use firmware to test FX3.

            After FX3 is powered on, I wired to FPGA and used FPGA logic analyzer to see the output signal of FX3.

            I found that the FlagA signal has always been "H". I just watched the FlagC signal and it will continue to have irregular "H" "L" conversions.

            I want to know if the FX3 hardware settings are wrong or other problems.

             

            • 3. Re: FX3 sends data to FPGA with FlagA problem
              RashiV_61

              Hello,

               

              From your description it seems that the FX3 is in boot loader mode.

              Please refer to section 11 of this https://www.cypress.com/file/201991/download application note which mentions the state of I/O when FX3 is in boot loader mode

               

              You need to program FX3 with the firmware attached with AN65974 application note to see the flag values

               

              Regards,

              Rashi

              1 of 1 people found this helpful
              • 4. Re: FX3 sends data to FPGA with FlagA problem
                YaZh_4656101

                Hello,

                I read your reference file and I also think my FX3 in boot loader mode.

                I have tried some operations.

                I used the "USB Suite" example(USBBulkLoopAuto) and program it to FX3 with "USB Control Center"(Program→FX3→RAM).

                I tested that "Bulk out endpoint (0x01)" can send data and "Bulk in endpoint (0x81)" can receive data, but the flag signal and other control signals remain unchanged, and the data is not sent to the FPGA.

                This operation can program the firmware into FX3, but still can't enable FX3.

                I want to know how to enable FX3 or which firmware should be program into FX3.

                Hope you can tell me the steps in more detail.

                Thanks!

                 

                 

                USB_Control_Center.JPG

                • 5. Re: FX3 sends data to FPGA with FlagA problem
                  RashiV_61

                  Hello,

                   

                  Bulkloopauto FX3 example firmware is to implement a data loopback application over a pair of USB bulk endpoints.

                   

                  The device enumerates as a vendor specific USB device with a pair of bulk endpoints (1-OUT and 1-IN).  The application loops back any data that it receives on the bulk OUT endpoint on the bulk IN endpoint.

                   

                  For FPGA to USB or USB to FPGA transfer. You need to use slavefifosync firmware attached with the application note AN65974 (AN^5974.zip)

                  https://www.cypress.com/documentation/application-notes/an65974-designing-ez-usb-fx3-slave-fifo-interface

                   

                   

                  Please refer to the GPIF interface and probe the GPIO's which are used as flags

                  slavefifo_an.PNG

                   

                  So try programming FX3 with this firmware (Path:..\001-65974_AN65974 \AN65974\FX3 Firmware\SlaveFifoSync\Release\SlaveFifoSync.img) and probe appropriate flags

                   

                  Regards,

                  Rashi

                  1 of 1 people found this helpful
                  • 6. Re: FX3 sends data to FPGA with FlagA problem
                    zeLu_283996

                    Hi, I bought two superspeed kits, one works fine, but another doesn't, which has the same problem for FlagA. When I changed FlagA from GPIO_21 to GPIO_22, It works fine. It may have  hardware problem.

                    • 7. Re: FX3 sends data to FPGA with FlagA problem
                      YaZh_4656101

                      Hello,

                      Thank you for your file. FX3 can change flag signal.

                      I use the firmware and Verilog Code from you provided, and FPGA can receive data.

                      But flag and other signal is weird,and there is a problem receiving the data of USB_DATA.

                      I sent usb_data.

                      12333.JPG

                       

                      received data by FPGA.

                      FPGA.jpg

                      The green circle indicates that the data received is correct.

                      The red circle indicates that the data received is wrong.

                      E.g:

                      The data received should be 0x03020100, but received is 0x00020100.

                      The data received should be 0x07060504, but received is 0x07060500.

                      The next data is correct(0x0B0A0908 and 0x0F0E0D0C) .

                      After that, the "sloe" and "slrd" signals became 1 and the data was wrong(Clock from 6 to 46).

                      Clock from 47 to 49 is correct(0x13121110 and 0x17161514).

                      Clock from 49 to 69 is wrong.

                      Clock from 69 to 70:data received should be 0x1B1A1918, but received is 0x1B1A1818.(flag_c is 1)

                      Clock from 70 to 142 is wrong.

                      data is missing 0x1F1E1D1C.

                      next data received should be 0x23222120, but received is 0x20222100.

                      next data received should be 0x27262524, but received is 0x27262520.

                      Clock from 144 to 146 is correct( 0x2B2A2928 and 0x2F2E2D2C.)

                      next data received should be 0x33323130, but received is 0x3F363D34.

                      next data received should be 0x37363534, but received is 0x37363530.

                      next data received should be 0x3B3A3938, but received is 0x3B3E3938.

                      next data received should be 0x3F3E3D3C, but received is 3F3A3D3C.

                      .......etc.

                      Every time I send the same data(00~5F), and FPGA receive the same wrong character.

                      I do n’t know what went wrong, the error rate is very high, but I found the Flag signal was unstable.

                      • 8. Re: FX3 sends data to FPGA with FlagA problem
                        RashiV_61

                        Hello,

                         

                        Please let me know how are the switch on spartan configured to configure the FPGA in one of the four FPGA transfer modes mentioned in table 6 of section 11.5

                         

                        Regards,

                        Rashi

                        • 9. Re: FX3 sends data to FPGA with FlagA problem
                          YaZh_4656101

                          Hello,

                          The FPGA board model I use is DE10-standard.

                          It seems that no switch in the table 6 of section 11.5 can be set.

                          • 10. Re: FX3 sends data to FPGA with FlagA problem
                            RashiV_61

                            Hello,

                             

                            If you are not using Spartan 6 or Altera FPGA, you need to modify the verilog code to switch between the FPGA transfer modes.

                            As per the state machine running on FPGA, if the modes are not switched, the FPGA will be in idle mode

                            modes.PNG

                            In default verilog/VHDL code, the status of the switch (on Spartan6 or Altera board) will decide the FPGA transfer mode. so please modify the FPGA code and then check the Data transfer as per the mode

                             

                            Please refer to this table and transfer the data accordingly. For USB> GPIf (FPGA) transfer Stream Bulk OUT mode needs to be chosen. for this the Full packets needs to be sent through USB. 512 bytes for USB 2.0 and 1024 bytes for USB 3.0. also in the firmware the macro STREAM_IN_OUT needs to be enabled

                             

                            table6.PNG

                             

                            Regards,

                            Rashi

                            • 11. Re: FX3 sends data to FPGA with FlagA problem
                              YaZh_4656101

                              Hello,

                              If I want to use Stream OUT mode, do I need to use other signals to trigger?

                              2020-03-28_160729.jpg

                              Or I need to modify the verilog code for the switch?

                              I use the "Stream OUT" example code for transmission testing, but the flag is very unstable, resulting in unstable data transmission.

                              So I want to have some ideas on how to modify the verilog code.

                              Thanks.

                              • 12. Re: FX3 sends data to FPGA with FlagA problem
                                RashiV_61

                                Hello,

                                 

                                In the verilog code (Path: ..\001-65974_AN65974 (3)\AN65974\FPGA Source files\fx3_slaveFIFO2b_xilinx\rtl_verilog\slaveFIFO2b)

                                - this is the top module slaveFIFO2b_fpga_top.v which has the input mode_p, based on the switched on the SPARTAN 6 board

                                mode.PNG

                                 

                                According to the status of these switches (on the SPARTAN 6 board) or the value of mode_p the FPGA transfer modes are switched and appropriate module is instantiated.

                                mode_1.PNG

                                 

                                So, the verilog coed need to be modified such that

                                next_fpga_master_mode = fpga_master_mode_stream_out;

                                 

                                and stream_out module instantiation is done

                                selction.PNG

                                 

                                STREAM_OUT transfer mode allows full packets to be transferred fro USB to FPGA i.e. for USB 2.0 packet size will be 512 bytes and for USB 3.0 packet size will be 1024 bytes. So please try sending full packet data after modifications to verilog code.

                                 

                                 

                                If I want to use Stream OUT mode, do I need to use other signals to trigger?

                                >> Only instantiation of slaveFIFO2b_streamOUT module need to be confirmed. No other triggers are required.

                                 

                                - Please program the FX3 first and then the FPGA

                                - Also check the FLAG status before transferring data (after programming FX3 and then FPGA)  and let me know the results

                                 

                                Regards,

                                Rashi

                                1 of 1 people found this helpful
                                • 13. Re: FX3 sends data to FPGA with FlagA problem
                                  YaZh_4656101

                                  Hello,

                                  I have some questions after reading the code.

                                   

                                  The board I used is Altera DE10-standard and my input clock is 50MHz.

                                  2020-03-30_203020.jpg

                                  But the code's PLL module input clock is 27Mhz to 100MHz, so do I need to regenerate a new PLL module with 50MHz to 100MHz?

                                  2020-03-30_203838.jpg

                                   

                                  What's the purpose of this module? I can't find the code of this module(ODDR2.v)  in the folder.

                                  Can I use the inversion of the PLL output clock(~clk_100) as clk_out?

                                  2020-03-30_204710.jpg

                                   

                                   

                                  I want to use Stream OUT mode,so should I changed "mode <= mode_p" to "mode <= STREAM_OUT"?

                                  Or is there other way to make the input signal "mode_p" become STREAM_OUT?

                                  2020-03-30_205712.jpg\

                                  2020-03-30_205956.jpg

                                   

                                  Thanks!

                                   

                                   

                                  • 14. Re: FX3 sends data to FPGA with FlagA problem
                                    RashiV_61

                                    Hello,

                                     

                                    But the code's PLL module input clock is 27Mhz to 100MHz, so do I need to regenerate a new PLL module with 50MHz to 100MHz?

                                    >> The 27MHz to 100MHz PLL is used as clk out is kept as 100 MHz to use the maximum data throughput of GPIF II interface. GPIF II can support frequency of 100 MHz. You can use different PLL but it would be to keep the clkout near to 100MHz to get higher data throughput.

                                     

                                    What's the purpose of this module? I can't find the code of this module(ODDR2.v)  in the folder.

                                    Can I use the inversion of the PLL output clock(~clk_100) as clk_out?

                                    >> Please refer to this document https://www.xilinx.com/support/documentation/user_guides/ug381.pdf for ODDR2https://forums.xilinx.com/t5/General-Technical-Discussion/Question-about-ODDR2/td-p/591355

                                    Solved: Question about ODDR2 - Community Forums

                                     

                                    I want to use Stream OUT mode,so should I changed "mode <= mode_p" to "mode <= STREAM_OUT"?

                                    Or is there other way to make the input signal "mode_p" become STREAM_OUT?

                                    >> yes, you can assign  3'd4/ STREAM_OUT to mode

                                     

                                     

                                    Regards,

                                    Rashi

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