5 Replies Latest reply on Mar 18, 2020 5:31 AM by LePo_1062026

    Clock module instantiation in Verilog (BUS_CLK)

    BoTa_264741

      Hi,

      I  made a custom component with simple Verilog code. Typically, a clock can be provided to the component externally, but I want to add internal BUS_CLK wire by instantiating a Clock module inside the Verilog code, but I can't find proper way to do this. For example, this code might work if proper object ID for clock is obtainable elsewhere (e.g. "66f6530c-badf-4eb8-b791-64ae7ecd409d").

       

      wire bus_clock_out;

       

      //instantiate BUS_CLK

      cy_clock_v1_0 #(

            .id("66f6530c-badf-4eb8-b791-64ae7ecd409d"),

            .source_clock_id(""),

            .divisor(0),

            .period("0"),

            .is_direct(1),

            .is_digital(1))

      Clock_ABC

           (.clock_out(bus_clock_out));

       

       

      Q: is there a regular way to instantiate a clock in Verilog?

      sincerely,

      /odissey1

        • 1. Re: Clock module instantiation in Verilog (BUS_CLK)
          LePo_1062026

          /odissey,

           

          It's been 5 days and no answer.  You're asking an involved question that requires significant knowledge of Verilog.  I'm afraid I'm not your candidate since I'm a neophyte in that regards.

           

          I thought Verilog syntax was mostly "valueless".  In other words it defines relationships between circuit elements that include net connections and timing for latches and the such. 

           

          Aren't clocks normally defined as inputs?  How do some of Cypress Verilog primitives instantiate required clocks?

           

          Len

           

          PS:  Sorry.  I'm probably not being helpful.

          • 2. Re: Clock module instantiation in Verilog (BUS_CLK)
            BoTa_264741

            Len,

            Clocks are usually an input to the component, but it shouldn't be a problem to have a BUS_CLK inside a component. Having  the clock outside is simple solution as its Verilog code is generated by the Customizer automatically. The Customer also obtains this lengthy  GUID number for the clock instance. I was hoping for some shortcut here, as all I need is a BUS_CLK.

             

            The alternative is to make a "core" component and encapsulate it in a "shell" component along with the clock. This is not as neat requiring the "core" to be hanging around, because Creator doesn't allow for nested components. This is OK for large components (Timer, etc.), but seems unnatural for a primitives, which I am trying to construct.

            /odissey1

            • 3. Re: Clock module instantiation in Verilog (BUS_CLK)
              LePo_1062026

              /odissey,

               

              Interesting.  You said:

              The alternative is to make a "core" component and encapsulate it in a "shell" component along with the clock. This is not as neat requiring the "core" to be hanging around, because Creator doesn't allow for nested components.

              I'm finishing up the next release of my "Term" component which nests the UART and USBUART components one level down.

               

              I do agree that Creator doesn't fully inherit properties at the lower customizer level.

               

              Len

              • 4. Re: Clock module instantiation in Verilog (BUS_CLK)
                BoTa_264741

                Len,

                In your case both the UART and USBUART components are part of Cypress default package. In my case I have to make an extra basic component alongside the main component and keep them together. Not neat.

                /odissey1

                • 5. Re: Clock module instantiation in Verilog (BUS_CLK)
                  LePo_1062026

                  /odissey1,

                   

                  Got it.  I wish could be of more help here.

                   

                  Len