2 Replies Latest reply on Mar 11, 2020 12:15 AM by MiYa_4339256

    s70fs01gs clarification for CR1V QUAD bit behavior after CR2V QPI bit set to 1

    MiYa_4339256

      Hi Expert,

       

      Please help clarify the CR1V QUAD bit behavior after CR2V QPI bit set to 1.

       

      There are two descriptions in the datasheet as below:

      1. From spec the CR1V description: "The QUAD bit must be set to one when using the Quad I/O Read, DDR Quad I/O Read, QPI mode (CR2V[6] = 1), and Read Quad ID commands."

      2. From spec the CR2V description: "When this bit is set to QPI mode, the QUAD bit is also set to Quad mode (CR1V[1]=1). When this bit is cleared to legacy SPI mode, the QUAD bit is not affected."

      So from the CR1V description, seems like the CR1V QUAD bit needs to be set '1' before set CR2V QPI bit to '1'.

      From the CR2V description, seems like the CR1V QUAD bit needs to be set to '1' automatically when CR2V QPI bit set to '1'.

       

      Which is the correct behavior for the CR1V QUAD bit after the CR2V QPI is set to '1' by WRAR (71h) command?

       

      Thanks,

      Mike