I wonder if what you are thinking is something like
In the Component Catalog > Digital > Logic
There are almost all basic logical gate, like And, Nand, Nor, Not, Or, Xnor, Xor.
So you can create almost any kind of combination(s).
Or may be you can create a UDB function to fulfill your logic requirement(s).
No, because that would not tell me which signal changed.
Basically, I want to capture the timer count when In1 changes, and the timer count when In2 changes, but I want them to be using the same timer so that I can compare the times that the two events occurred.
That's not capturing signals from multiple inputs; it's counting multiple events on a single input. As the datasheet says:
Enable Capture Counter (Software Option)
The Enable Capture Counter parameter is used to define how many capture events happen before the counter is actually captured. For example, it may be necessary to capture every third event, in which case the capture counter must be set to a value of 3. This parameter is only available for a UDB implementation.\
Capture Count (Software Option)
The Capture Count parameter sets the initial number of capture events that occur before the counter is actually captured. It can be set to a value from 2 to 127. The capture count value may be modified at run time by calling the API function Timer_SetCaptureCount(). This parameter is only available for a UDB implementation.
On Capture (1-4) – Allows you to interrupt on a given number of captures; it is cleared by default.
So I wrote
> But it may not be easy to tell which pin asserted first.
> So you may need additional circuit to distinct them.
Probably the timer can hold times of up to 4 events.
Then if you need to know which signal was asserted you need to provide a mechanism to save the status of pin at the event.
Following is only off my head idea/sketch, there could be many better ways, but just to show that there must be ways to accomplish the task.
May be this is going to be wordy though, a couple of DFFs and AND gate and NOT gate can compose a rising edge detector. Then "OR"ing a couple of edge detect signals can be used to trigger a timer capture and trigger an interrupt to let the software store current input values so that later we can find which signal caused which event.
I came across this which might be useful: https://www.cypress.com/file/227156/download "Time-Stamped ADC Data Transfer Using DMA".
It's an app note about capturing A/D with time stamps. If I have my digital inputs coming into a sticky status register, use XOR gates to detect differences between the sticky data and the current data, and have that trigger the DMA to capture both the data and the timestamp, that might do it.
What is the size of the timer you need? 7-bits, 8-bits, 16-bits?
For the two inputs, are you trying to capture the rising, falling or either edges?
Here's a schematic of a circuit where either or both edges of in_1 triggers a DMA_1 event which takes the captured count in Timer_1 and places it into RAM. The DMA can be configured for a single capture burst and the nrq terminal can trigger the isr_capture_done_in_1 to inform the CPU a capture has occurred on in_1.
The same thing can occur with in_2, DMA_2 and isr_capture_done_in_2 into a different part of RAM.