I wish that API files could be enabled based on some parameters, but AFAIK, Creator does not have this feature. However, it is possible to create separate API and schematic files targeting different PSoC models PSoC3 / PSoC4 / PSoC5 (using a checkmark when adding a component item).
Typically, code inside API files can be selectively enabled/disabled using structure
The automatically generated header "project.h" is something like
So, although this may not be a recommended method,
if you copy the "project.h" to your local folder, such as where main.c is resides,
and rename it something like "my_project.h" and comment out
#include line of you don't need will disable that component.
Then include "my_project.h" instead of "project.h" may do what you want to do.
And needless to say, please proceed at your own risk.
Another method I can think of is, preparing multiple schematics
and enable/disable each schematics before compiling may also do what you want.
Thank you. I've evaluated both of your recommendations.
I'm trying to create a forum-sharable component. Your "project.h" approach requires extra work on the user of the component.
I've have previously implemented your multiple schematic approach. The problem I ran into was that when I wanted to pass parameter data from the top-level of the component to the lower-level components some of the parameter data was altered by the lower-level component custom .cs call.
Thanks for your help.
I may need to use your #if () ... #elif () ... #endif approach.
What I'm trying to do is modify my "Term" component that I released in the Code sharing area (Terminal Component - Simplifies UART or USBUART communication ) to allow for a nearly transparent interface to the UART function if the UART type is selected. This includes all the code and IO configuration.
At first I tried to accomplish this by passing user configuration parameters to the lower-level Cypress UART V2.50 release component. It generally worked however there were a few parameters that reverted to default parameter values instead of the definition expressions I provided. (This was because during development the underlying custom .cs files found the expression value and pushed the default values in the value field.)
Therefore I elected to substitute the BUART primitive and copy the UART API files direclty to my new component's API directory. My goal was to conditionally include these UART API files if the user selects UART as the Term Type but not include them when selecting USBUART.
> I've evaluated both of your recommendations.
Oh, I see. You've been much farther.
If you find some good methods, please share them with us ;-)
Moto and /odissey1,
I have a related question about Verilog that might apply to what I'm trying to accomplish on this post discussion.
Is it possible to create a Verilog component definition that has one input and one output. In most cases the input is passed to the output directly.
However if during the Application Build phase if the input is not connected that the Verilog definition will assign the output with a default value.
I've tried this and found the Application Build is not completed. It complains about an unconnected input. Is there a Verilog compilation instruction that detects this unconnected input and reassigns it to a default value? I'm a bit new to Verilog and the information I have read about it does not easy define compile warnings/errors asserts very well.
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On the input terminal, Format Shape->Default Value=8'b0. Must connect when visible = true/false (check one which works, but I may be irrelevant).
Somehow, this often helps.
I'm trying to use the Cypress UART component inside my Term component.
For example when I select FlowControl = Hardware, rts_n shows up and I connect it to an output pin to expose to my Term symbol.
However, if I select FlowControl = None, rts_n goes away and the internal schematic for Term on this pin looks like this:
This gives me an error that rts_n has no drivers. And the Build aborts.
I tried to add an custom component using Verilog called "passthru".
The goal of "passthru" was to pass the signal through but if the input to "passthru" was not connected to an output, to default to '0'.
Verilog is now complaining that the input to "passthru" is unconnected. I was wondering if there were some Verilog compile capabilities to sense the unconnected input and assign it to a default value.
Your suggestion about the "Default value" and "Must connect when Visible" appears to work on my "passthru" component.
Here's what I did to solve the issue.
The issue: The component output pins at the schematic level of the component DO NOT like to be unconnected! Additionally, there is no way to ignore or quiet this issue from the standard pin definition.
I created a VERY simple component with one input and one output called "passthru". It passes the signal directly from the input to the output.
Here's the "passthru" schematic. VERY SIMPLE. A wire. (Dah!)
The trick to make this work is to make sure the input pin of the symbol "passthru" has the following changes:
- Select the input pin and "Format Shape"
- Default Expression = 1'b0 ('0' is the default value for the input)
- Must Connect if Visible = False
I can now build without errors even if the input to passthru is unconnected upstream.