4 Replies Latest reply on Mar 11, 2020 9:16 AM by PSa_795526

    Configuring pull up and pull down resistors on an analog input pin

    ErPi_4599236

      I am trying to read the status of an MCP73831 LiPo charge controller. The data sheet gives the following table for its three states (shutdown, charging, and complete):

      I would like to be able to identify each condition as it occurs. My hardware has already been designed for me, and we are trying to avoid another round of revisions. A solution I came up with was to configure the controller's status pin (see table above) to an analog input on my PSoC 4 (CY8C4127LQI-BL453) configured with internal pull up and pull down resistors. This would allow for me to detect when the charge controller's status pin goes high (Vdd), low (GND), or Hi-Z (Vdd / 2).

       

      But, I'm having trouble getting the results I expect. I found this recent thread and followed it directly (only with both pull up and pull down chosen):

       

      https://community.cypress.com/thread/43322?q=Configuring%20pull%20up%20and%20pull%20down%20resistors%20on%20an%20analog

       

      However, even when assigning this configuration to an unused pin, which I would expect to act as my Hi-Z (Vdd / 2) state, I am reading Vdd.

       

      Below is my configuration:

       

      And code:

       

       

      Any obvious suggestions? Is what I'm attempting even possible?

        • 1. Re: Configuring pull up and pull down resistors on an analog input pin
          LinglingG_46

          I write a simple project to test the function. And I attached the test project in attachment.

          After review your codes, I think you should wait for the ending of the convert of ADC, then start to read the result.

          Like:

            while(0u != ADC_IsEndConversion(CY_SAR_RETURN_STATUS))

                {;}

          I don't use the continuous mode, use single mode.

          • 2. Re: Configuring pull up and pull down resistors on an analog input pin
            ErPi_4599236

            Thank you for your response, Lingling. I can't seem to open this project file. Can you recommend the version of IDE you used to develop this? I'm also having trouble referencing the CY_SAR_RETURN_STATUS definition.

             

            I am currently using PSoC Creator 4.2 with the CY8C4127LQI-BL453 chip.

            • 3. Re: Configuring pull up and pull down resistors on an analog input pin
              LinglingG_46

              As my understanding, it could be use this way to test the VDD:

              https://community.cypress.com/thread/43322?q=Configuring%20pull%20up%20and%20pull%20down%20resistors%20on%20an%20analog

               

              But I can't understand why do you want to test the Analog High Z? In addition, I think it is unreasonable to say that the Analog high z is equal to vdd/2.

              Why don't you use the voltage divider to test the voltage?

               

              • 4. Re: Configuring pull up and pull down resistors on an analog input pin
                PSa_795526

                Hi,

                The resistive pull up/down drive mode does not imply a Vdd/2 potential divider at the pin. It only means that both logic low and logic high are resistive (not strong). Since only one logic can be driven at any point of time(either logic high or low), only one resistor appears at any point of time, and the other resistor is floating. During logic HIGH is, only the upper PMOS is ON and the lower NMOS is OFF in the pin driver. Similarly, during logic LOW, the PMOS is OFF and NMOS is ON.

                 

                However, your requirement (of detecting a logic HIGH/LOW/Hi-Z) can be met by dynamically changing the pin output drive(logic HIGH/LOW) and reading the pin status(or ADC value) twice.

                If the pin is left Hi-Z externally, then the pin status(or ADC value) will change based on the logic driven from inside PSoC.

                If the pin is at logic high/low externally, then the pin status(or ADC value) will stay the same(as the externally driven logic) irrespective of whether logic high or low is driven from inside PSoC(because the external strong drive overrides the internal resistive drive). Thereby the 3 states (logic HIGH/LOW/Hi-Z) of the pin can be detected.

                 

                Since only logic low/high has to be read for this technique, reading Pin status is sufficient and ADC value is not necessary.

                Configure the pin as shown in image:

                - Keep the drive mode as resistive pull up/down.

                - Check both digital input and output check boxes.

                - Uncheck the HW connection, so that pin drive logic can be dynamically changed in firmware.

                In firmware:

                - First drive the pin logic High (using Pin_Write()), and read the pin status(using Pin_Read()).

                - Then drive the pin logic Low and read the pin again.

                 

                If the pin status reads high both times, it implies pin is at logic HIGH externally.

                If the pin status reads low both times, it implies pin is at logic LOW externally.

                If the pin status reads high when written high and low when written low, it implies pin is at Hi-Z externally.

                 

                Best Regards,

                Prem Sai

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